<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/amd/display/dc/bios, branch linux-5.0.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.0.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.0.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2018-12-18T22:39:56Z</updated>
<entry>
<title>drm/amd/display: Add functionality to get XGMI SS info</title>
<updated>2018-12-18T22:39:56Z</updated>
<author>
<name>Leo Li</name>
</author>
<published>2018-10-31T21:07:41Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1c01a45a86ed6991953e74be63b6a7e33b387954'/>
<id>urn:sha1:1c01a45a86ed6991953e74be63b6a7e33b387954</id>
<content type='text'>
[Why]
When XGMI is enabled, the DP reference clock needs to be adjusted
according to the XGMI spread spectrum percentage and mode. But first,
we need the ability to fetch this info.

[How]
Within the BIOS parser, Read from vBIOS when XGMI SS info is requested.

In addition, diags build uses include_legacy/atomfirmware.h for the
smu_info_v3_3 table headers. Update that as well.

Signed-off-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DCE_VERSION_12_1 enum for Vega 20</title>
<updated>2018-12-18T22:39:49Z</updated>
<author>
<name>Leo Li</name>
</author>
<published>2018-10-31T20:56:54Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b8b6ce89016485cb92fdf2f527b40249aefbc470'/>
<id>urn:sha1:b8b6ce89016485cb92fdf2f527b40249aefbc470</id>
<content type='text'>
[Why]
We'll need a way to differentiate Vega 20 in DC

[How]
Add a DCE_VERSION_12_1 enum, which will be returned as the DC version if
the ASIC used is a Vega 20.

Signed-off-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Reviewed-by: David Francis &lt;David.Francis@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add condition to sync eDP SW status and HW status</title>
<updated>2018-11-05T19:21:45Z</updated>
<author>
<name>Lewis Huang</name>
</author>
<published>2018-10-18T09:52:19Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d2b1d6bbc56afab8ebae9d52d7ca0ea3569bd600'/>
<id>urn:sha1:d2b1d6bbc56afab8ebae9d52d7ca0ea3569bd600</id>
<content type='text'>
[Why]
Need to disable EDP backlight when enter S4 with EDP only
and resume from S4 with secondary only.

[How]
Align the real hw and sw state via vBios scratch register in
function enable_accelerated_mode when resume from S4.

Signed-off-by: Lewis Huang &lt;Lewis.Huang@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix up coverity issues</title>
<updated>2018-11-05T19:21:35Z</updated>
<author>
<name>Aric Cyr</name>
</author>
<published>2018-10-10T23:02:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=69133b89359120e741dff3e09dcfdc08ff954445'/>
<id>urn:sha1:69133b89359120e741dff3e09dcfdc08ff954445</id>
<content type='text'>
[Why]
Coverity found various high-impact issues that need resolving.

[How]
Fix  some buffer overruns and uninitialized variables.

Signed-off-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add Raven2 definitions in dc</title>
<updated>2018-09-14T14:36:47Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
</author>
<published>2018-01-22T21:12:27Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=0e3d73f1a440eaca270a028bff51649ae99df113'/>
<id>urn:sha1:0e3d73f1a440eaca270a028bff51649ae99df113</id>
<content type='text'>
Add Raven2 definitions in the dc code

Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: remove dead dc vbios code</title>
<updated>2018-09-11T03:42:46Z</updated>
<author>
<name>Dmytro Laktyushkin</name>
</author>
<published>2018-08-14T20:12:54Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5a8132b9f6063b36369b2afd85112ff37d56e183'/>
<id>urn:sha1:5a8132b9f6063b36369b2afd85112ff37d56e183</id>
<content type='text'>
Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Create new i2c resource</title>
<updated>2018-08-27T16:11:05Z</updated>
<author>
<name>David Francis</name>
</author>
<published>2018-07-23T18:12:10Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c85e6e546edd7e362693218a33a6f63217802fd3'/>
<id>urn:sha1:c85e6e546edd7e362693218a33a6f63217802fd3</id>
<content type='text'>
[Why]
I2C code did not match dc resource model and was generally
unpleasant

[How]
Move code into new svelte dce_i2c files, replacing various i2c
objects with two structs: dce_i2c_sw and dce_i2c_hw.  Fully split
sw and hw code paths.  Remove all redundant declarations.  Use
address lists to distinguish between versions.  Change dce80 code
to newer register access macros.

Signed-off-by: David Francis &lt;David.Francis@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Set DFS bypass flags for dce110</title>
<updated>2018-08-27T16:09:49Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
</author>
<published>2018-07-24T17:19:49Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=4e60536d093f486229bb8d86c739e8ef6446df85'/>
<id>urn:sha1:4e60536d093f486229bb8d86c739e8ef6446df85</id>
<content type='text'>
[Why]

While there is support for using and quering DFS bypass clocks the
hardware is never notified to enter DFS bypass mode for dce110.

[How]

Add a flag that can be set when programming the display engine PLL
to enable DFS bypass mode. If this flag is set then the hardware is
notified to enter DFS bypass mode and the correct display engine clock
frequency can be acquired.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Revert "drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86"</title>
<updated>2018-08-21T19:32:28Z</updated>
<author>
<name>Leo (Sunpeng) Li</name>
</author>
<published>2018-08-16T19:44:38Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=dc37a9a08d5760e405ffdd94ec6bbb6efededba6'/>
<id>urn:sha1:dc37a9a08d5760e405ffdd94ec6bbb6efededba6</id>
<content type='text'>
This reverts commit 8624c3c4dbfe24fc6740687236a2e196f5f4bfb0.

We need CONFIG_DRM_AMD_DC_DCN1_0 to guard code that is using fp math.

Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Leo (Sunpeng) Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: update clk for various HDMI color depths</title>
<updated>2018-08-06T20:57:29Z</updated>
<author>
<name>Mikita Lipski</name>
</author>
<published>2018-07-13T13:07:35Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=81aca8e75c1b046865fb2badef95a0dcff6f73de'/>
<id>urn:sha1:81aca8e75c1b046865fb2badef95a0dcff6f73de</id>
<content type='text'>
[why]
When programming tonga's connector's backend we didn't take
in account that HDMI's colour depth might be more than 8bpc
therefore we need to add a switch statement that would adjust
the pixel clock accordingly.

[how]
Add a switch statement updating clock by its appropriate
coefficient.

Signed-off-by: Mikita Lipski &lt;mikita.lipski@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
</feed>
