<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/amd/display/dc/Makefile, branch linux-5.13.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.13.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.13.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2021-04-09T20:48:38Z</updated>
<entry>
<title>drm/amd/display: Add dynamic link encoder selection.</title>
<updated>2021-04-09T20:48:38Z</updated>
<author>
<name>Jimmy Kizito</name>
</author>
<published>2021-01-05T19:25:23Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f42ef862fb1fbbd291fb381f38d3910da644a44d'/>
<id>urn:sha1:f42ef862fb1fbbd291fb381f38d3910da644a44d</id>
<content type='text'>
[Why]
Some display endpoints may be programmably mapped to compatible link
encoders. The assignment of link encoders to links has to be dynamic to
accommodate the increased flexibility in comparison to conventional
display endpoints.

[How]
- Add link encoder assignment tracking variables.
- Execute link encoder assignment algorithm before enabling link and
release link encoders from links once they are disabled.

Signed-off-by: Jimmy Kizito &lt;Jimmy.Kizito@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Anson Jacob &lt;Anson.Jacob@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Support for DMUB AUX</title>
<updated>2021-03-02T19:05:41Z</updated>
<author>
<name>Meenakshikumar Somasundaram</name>
</author>
<published>2021-01-22T06:25:56Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=4f8e37dbaf584de6d38f58b3000b0bfd7eaf2ff6'/>
<id>urn:sha1:4f8e37dbaf584de6d38f58b3000b0bfd7eaf2ff6</id>
<content type='text'>
[WHY]
To process AUX transactions with DMUB using inbox1 and outbox1 mail boxes.

[HOW]
1) Added inbox1 command DMUB_CMD__DP_AUX_ACCESS to issue AUX commands
   to DMUB in dc_process_dmub_aux_transfer_async(). DMUB processes AUX cmd
   with DCN and sends reply back in an outbox1 message triggering an
   outbox1 interrupt to driver.
2) In existing driver implementation, AUX commands are processed
   synchronously by configuring DCN reg. But in DMUB AUX, driver sends an
   inbox1 message and waits for a conditional variable (CV) which will be
   signaled by outbox1 ISR.
3) As the driver holds dal and dc locks while waiting for CV, the outbox1
   ISR is registered with noMutexWait set to true, which allows ISR to run
   and signal CV. This sets a constraint on ISR to not modify variables
   such as dc, dmub, etc.
4) Created dmub_outbox.c with dmub_enable_outbox_notification() to enable
   outbox1 mailbox.
5) New mailbox address ranges allocated for outbox1 of size DMUB_RB_SIZE.
   Created dmub functions for Outbox1: dmub_dcn20_setup_out_mailbox(),
   dmub_dcn20_get_outbox1_wptr() and dmub_dcn20_set_outbox1_rptr().
6) Added functions dc_stat_get_dmub_notification() and
   dmub_srv_stat_get_notification() to retrieve Outbox1 message.
7) Currently, DMUB doesn't opens DDC in AUX mode before issuing AUX
   transaction. A workaround is added in dce_aux_transfer_dmub_raw() to
   open in DDC in AUX mode for every AUX transaction.
8) Added dc debug option enable_dmub_aux_for_legacy_ddc enable/disable
   DMUB AUX. This debug option is checked dce_aux_transfer_with_retries()
   to select the method to process AUX transactions.

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Meenakshikumar Somasundaram &lt;meenakshikumar.somasundaram@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add Freesync HDMI support to DMCU</title>
<updated>2021-02-02T17:11:41Z</updated>
<author>
<name>Stylon Wang</name>
</author>
<published>2020-12-04T04:08:31Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a0c898f28a3b6d97d425aafc56085c273e9f1cff'/>
<id>urn:sha1:a0c898f28a3b6d97d425aafc56085c273e9f1cff</id>
<content type='text'>
[Why]
Adding support for Freesync HDMI to DC and DMCU

[How]
Create DC interface and implementation on top of DMCU to support
parsing CEA blocks in DMCU.

Signed-off-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Reviewed-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Acked-by: Anson Jacob &lt;Anson.Jacob@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)</title>
<updated>2020-11-04T22:11:37Z</updated>
<author>
<name>Alex Deucher</name>
</author>
<published>2020-11-02T20:37:34Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=20f2ffe504728612d7b0c34e4f8280e34251e704'/>
<id>urn:sha1:20f2ffe504728612d7b0c34e4f8280e34251e704</id>
<content type='text'>
Avoids confusion in configurations.

v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled
v3: rebase on latest code

Reviewed-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt; (v1)
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add support for DCN302 (v2)</title>
<updated>2020-10-12T18:02:51Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
</author>
<published>2020-09-29T18:52:09Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=36d26912e8d854853e3cdb300664db274a6636cf'/>
<id>urn:sha1:36d26912e8d854853e3cdb300664db274a6636cf</id>
<content type='text'>
 - add DCN302 resource, irq service, dmub loader,
 - handle  DC_VERSION_DCN_3_02
 - define DCN302 power gating functions
 - handle DCN302 in GPIO files
 - define I2C regs
 - add CONFIG_DRM_AMD_DC_DCN3_02 guard

v2: rebase fixes (Alex)

Signed-off-by: Joshua Aberback &lt;joshua.aberback@amd.com&gt;
Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add dcn3.01 support to DC (v2)</title>
<updated>2020-10-05T19:15:56Z</updated>
<author>
<name>Roman Li</name>
</author>
<published>2020-09-29T15:21:58Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3a83e4e64bb1522ddac67ffc787d1c38291e1a65'/>
<id>urn:sha1:3a83e4e64bb1522ddac67ffc787d1c38291e1a65</id>
<content type='text'>
Update dc for vangogh support.

v2: fix compilation without DCN 301 set.

Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: dc/dce: add initial DCE6 support (v10)</title>
<updated>2020-07-27T20:45:51Z</updated>
<author>
<name>Mauro Rossi</name>
</author>
<published>2020-07-11T19:43:25Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7c15fd86aaec3e602e140c242369df2baddc865e'/>
<id>urn:sha1:7c15fd86aaec3e602e140c242369df2baddc865e</id>
<content type='text'>
[Why]
DCE6 chipsets have a lot in common with DCE8, let's start from this

[How]
DCE6 targets are added replicating existing DCE8 implementation.

NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
initial build prototype due to missing DCE6 macros/registers/masks
DCE6 specific macros/registers/masks will be added with later commits

(v2b) removed dce_version cases in dc/dce/dce_clock_source.c and
     updated dce60 due to following kernel 5.0 commits:
     24f7dd7 ("drm/amd/display: move pplib/smu notification to dccg block")
     9566b67 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead")
     4244381 ("drm/amd/display: clean up base dccg struct")
     4c5e8b5 ("drm/amd/display: split dccg clock manager into asic folders")
     84e7fc0 ("drm/amd/display: rename dccg to clk_mgr")
     77f6916 ("drm/amd/display: Remove duplicate header")
     9f7ddbe ("drm/amd/display: fix optimize_bandwidth func pointer for dce80")
     4ece61a ("drm/amd/display: set clocks to 0 on suspend on dce80")

(v3b) updated dce60 due to following kernel 5.1 commits:
     380604e ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks")
     32e6136 ("drm/amd/display: Fix 64-bit division for 32-bit builds")
     1877ccf ("drm/amd/display: Change from aux_engine to dce_aux")
     c69dffa ("drm/amd/display: fix eDP fast bootup for pre-raven asic")

(v4b) updated dce60 due to following kernel 5.2 commits:
     e5c4197 ("drm/amd/display: Add plane capabilities to dc_caps")
     813d20d ("drm/amd/display: Fix multi-thread writing to 1 state")
     ea36ad3 ("drm/amd/display: expand plane caps to include fp16 and scaling capability")
     afcd526 ("drm/amd/display: Add fast_validate parameter")

(v5b) updated dce60 due to following kernel 5.3 commits:
     e7e10c4 ("drm/amd/display: stop external access to internal optc sync params")
     78cc70b ("drm/amd/display: Engine-specific encoder allocation")
     dc88b4a ("drm/amd/display: make clk mgr soc specific")
     4fc4dca ("drm/amd: drop use of drmp.h in os_types.h")

(v6b) updated dce60 due to following kernel 5.4 commits:
     54a9bcb ("drm/amd/display: Fix a typo - dce_aduio_mask --&gt; dce_audio_mask")
     9adc805 ("drm/amd/display: make firmware info only load once during dc_bios create")

(v7b) updated dce60 due to following kernel 5.5 commits:
     cabe144 ("drm/amd/display: memory leak")
     8276dd8 ("drm/amd/display: update register field access mechanism")
     f6040a4 ("drm/amd/display: configurable aux timeout support")
     bf7f5ac ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x")

(v8b) updated dce60 due to following kernel 5.6 commits:
     d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs")
     f42ea55 ("drm/amd/display: add separate of private hwss functions")

(v9b) updated dce60 due to following kernel 5.8 commits:
     bba8289 ("drm/amd/display: code clean up in dce80_hw_sequencer.c")
     904fb6e ("drm/amd/display: move panel power seq to new panel struct")
     d4caa72 ("drm/amd/display: change from panel to panel cntl")

(v10) Fix up PLL handling for DCE6:
     DCE6.0 supports 2 PLLs.  DCE6.1 supports 3 PLLs. (Alex)

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Mauro Rossi &lt;issor.oruam@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DCN3 blocks to Makefile</title>
<updated>2020-07-01T05:59:15Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
</author>
<published>2020-05-25T17:18:16Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e77165bf7b02a3c01819a209c6c569850254c020'/>
<id>urn:sha1:e77165bf7b02a3c01819a209c6c569850254c020</id>
<content type='text'>
Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: rename DCN1_0 kconfig to DCN</title>
<updated>2019-11-13T20:29:44Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
</author>
<published>2019-11-06T19:48:35Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b86a1aa36a92bcfbc062c5e99c1d084f27f25bab'/>
<id>urn:sha1:b86a1aa36a92bcfbc062c5e99c1d084f27f25bab</id>
<content type='text'>
Since dcn20 and dcn21 are under dcn1 it doesnt make sense to
have it named dcn1.

Change it to "dcn" to make it generic

Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_1 flag</title>
<updated>2019-11-13T20:29:44Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
</author>
<published>2019-11-06T19:44:19Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=aca935c7cc866a935a61769c9e9782dd834a8502'/>
<id>urn:sha1:aca935c7cc866a935a61769c9e9782dd834a8502</id>
<content type='text'>
[Why]

DCN21 is stable enough to be build by default. So drop the flags.

[How]

Remove them using the unifdef tool. The following commands were executed
in sequence:

$ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DCN2_1 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_1 '{}' ';'
$ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DCN2_1 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_1 '{}' ';'

In addition:

* Remove from kconfig, and replace any dependencies with DCN1_0.
* Remove from any makefiles.
* Fix and cleanup Renoir definitions in dal_asic_id.h
* Expand DCN1 ifdef to include DCN21 code in the following files:
    * clk_mgr/clk_mgr.c: dc_clk_mgr_create()
    * core/dc_resources.c: dc_create_resource_pool()
    * gpio/hw_factory.c: dal_hw_factory_init()
    * gpio/hw_translate.c: dal_hw_translate_init()

Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
