<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c, branch linux-5.3.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.3.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.3.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2019-12-04T21:33:55Z</updated>
<entry>
<title>drm/amdgpu: register gpu instance before fan boost feature enablment</title>
<updated>2019-12-04T21:33:55Z</updated>
<author>
<name>Evan Quan</name>
</author>
<published>2019-11-05T10:13:49Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=bf2e5f0321247f4d6ce3f150f69f5d8bfb254066'/>
<id>urn:sha1:bf2e5f0321247f4d6ce3f150f69f5d8bfb254066</id>
<content type='text'>
[ Upstream commit 6a299d7aaa97dfde5988d8f9e2fa2c046b5793ff ]

Otherwise, the feature enablement will be skipped due to wrong count.

Fixes: beff74bc6e0fa91 ("drm/amdgpu: fix a race in GPU reset with IB test (v2)")
Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/psp: add a mutex to protect access to the psp ring</title>
<updated>2019-07-09T22:43:39Z</updated>
<author>
<name>Alex Deucher</name>
</author>
<published>2019-07-08T18:33:22Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=32eaeae0ef193b64a67177006bdf5d9130d83fd3'/>
<id>urn:sha1:32eaeae0ef193b64a67177006bdf5d9130d83fd3</id>
<content type='text'>
We need to serialize access to the psp ring if there are multiple
callers at runtime.

Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: properly guard the generic discovery code</title>
<updated>2019-07-09T22:43:31Z</updated>
<author>
<name>Alex Deucher</name>
</author>
<published>2019-07-08T18:44:59Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f54eeab4e7e066c6fd2f409f599f043c4ef98a6e'/>
<id>urn:sha1:f54eeab4e7e066c6fd2f409f599f043c4ef98a6e</id>
<content type='text'>
It's only available on navi and newer.

Reviewed-by: Xiaojie Yuan &lt;xiaojie.yuan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>amdgpu: make pmu support optional</title>
<updated>2019-07-08T18:56:22Z</updated>
<author>
<name>Arnd Bergmann</name>
</author>
<published>2019-07-08T14:41:43Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d155bef0636e019418ef5a69cafce129cc202b78'/>
<id>urn:sha1:d155bef0636e019418ef5a69cafce129cc202b78</id>
<content type='text'>
When CONFIG_PERF_EVENTS is disabled, we cannot compile the pmu
portion of the amdgpu driver:

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:48:38: error: no member named 'hw' in 'struct perf_event'
        struct hw_perf_event *hwc = &amp;event-&gt;hw;
                                     ~~~~~  ^
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:51:13: error: no member named 'attr' in 'struct perf_event'
        if (event-&gt;attr.type != event-&gt;pmu-&gt;type)
            ~~~~~  ^
...

Use conditional compilation for this file.

Fixes: 9c7c85f7ea1f ("drm/amdgpu: add pmu counters")
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Disable ras features on all IPs before gpu reset</title>
<updated>2019-07-05T20:59:20Z</updated>
<author>
<name>xinhui pan</name>
</author>
<published>2019-07-04T02:54:58Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f1c1314be4297183937fc2eab994be688425e328'/>
<id>urn:sha1:f1c1314be4297183937fc2eab994be688425e328</id>
<content type='text'>
Perform a ras_suspend to disable ras on all IPs to workaround
some ROCm stability issue.

Signed-off-by: xinhui pan &lt;xinhui.pan@amd.com&gt;
Acked-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable PCIE atomics ops support</title>
<updated>2019-07-01T19:54:40Z</updated>
<author>
<name>Jack Xiao</name>
</author>
<published>2019-05-23T16:13:14Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b2109d8ed6976569ba20da4db6eb64392ec7879d'/>
<id>urn:sha1:b2109d8ed6976569ba20da4db6eb64392ec7879d</id>
<content type='text'>
GPU atomics operation depends on PCIE atomics support.
Always enable PCIE atomics ops support in case that
it hasn't been enabled.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix MGPU fan boost enablement for XGMI reset</title>
<updated>2019-07-01T19:54:12Z</updated>
<author>
<name>Evan Quan</name>
</author>
<published>2019-06-26T02:53:39Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=fdafb3597a2cc46217d67bc68253024744af59b9'/>
<id>urn:sha1:fdafb3597a2cc46217d67bc68253024744af59b9</id>
<content type='text'>
MGPU fan boost feature should not be enabled until all the
devices from the same hive are all back from reset.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'drm-next' into drm-next-5.3</title>
<updated>2019-06-25T13:42:25Z</updated>
<author>
<name>Alex Deucher</name>
</author>
<published>2019-06-25T13:42:25Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d7929c1e13e3788e7cb741d75b5baec5e53eff21'/>
<id>urn:sha1:d7929c1e13e3788e7cb741d75b5baec5e53eff21</id>
<content type='text'>
Backmerge drm-next and fix up conflicts due to drmP.h removal.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable DC support for Navi10</title>
<updated>2019-06-22T14:34:07Z</updated>
<author>
<name>Harry Wentland</name>
</author>
<published>2019-02-26T21:25:27Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b4f199c7b00c87183f10c0a8f635f26ba2ede3eb'/>
<id>urn:sha1:b4f199c7b00c87183f10c0a8f635f26ba2ede3eb</id>
<content type='text'>
Enable the IP for navi10.

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Read soc_bounding_box from gpu_info (v2)</title>
<updated>2019-06-21T23:59:34Z</updated>
<author>
<name>Harry Wentland</name>
</author>
<published>2019-05-07T19:34:21Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=48321c3dde79f7f2db5000febddf70df3620c445'/>
<id>urn:sha1:48321c3dde79f7f2db5000febddf70df3620c445</id>
<content type='text'>
[WHY]
We don't want to expose sensitive ASIC information before ASIC release.

[HOW]
Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it
at driver load.

v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex)

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
