kernel.git/drivers/fpga/Kconfig, branch linux-4.15.y

fpga manager: Add Altera CvP driver

2017-07-17T15:26:15Z

Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V and Arria-10 FPGAs via CvP. Signed-off-by: Anatolij Gustschin Reviewed-by: Andy Shevchenko Signed-off-by: Alan Tull Signed-off-by: Greg Kroah-Hartman

fpga manager: Add altera-ps-spi driver for Altera FPGAs

2017-07-17T15:26:14Z

altera-ps-spi loads FPGA firmware over SPI, using the "passive serial" interface on Altera Arria 10, Cyclone V or Stratix V FPGAs. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional SPI with lsb first. Signed-off-by: Joshua Clayton Signed-off-by: Anatolij Gustschin Signed-off-by: Alan Tull Signed-off-by: Greg Kroah-Hartman

Make FPGA a menuconfig to ease disabling it all

2017-07-17T15:26:14Z

No need to get into the submenu to disable all FPGA-related config entries Signed-off-by: Vincent Legoll Acked-by: Moritz Fischer Signed-off-by: Alan Tull Signed-off-by: Greg Kroah-Hartman

fpga: Add support for Xilinx LogiCORE PR Decoupler

2017-04-08T15:50:36Z

This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration. Signed-off-by: Moritz Fischer Signed-off-by: Michal Simek Cc: Sören Brinkmann Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman

fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

2017-04-08T15:45:28Z

This adds a platform bus driver for a fpga-mgr driver that uses the Altera Partial Reconfiguration IP component. Signed-off-by: Matthew Gerlach Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman

fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

2017-04-08T15:45:28Z

Adding the core functions necessary for a fpga-mgr driver for the Altera Partial IP component. It is intended for these functions to be used by the various bus implementations like the platform bus or the PCIe bus. Signed-off-by: Matthew Gerlach Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman

fpga manager: Add Xilinx slave serial SPI driver

2017-04-08T15:45:28Z

The driver loads FPGA firmware over SPI, using the "slave serial" configuration interface on Xilinx FPGAs. Signed-off-by: Anatolij Gustschin Acked-by: Michal Simek Reviewed-by: Moritz Fischer Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman

fpga: Add support for Lattice iCE40 FPGAs

2017-03-17T06:10:48Z

This patch adds support to the FPGA manager for configuring the SRAM of iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40 UltraPlus devices, through slave SPI. Signed-off-by: Joel Holdsworth Reviewed-by: Marek Vasut Reviewed-by: Moritz Fischer Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman

FPGA: Add TS-7300 FPGA manager

2017-03-17T06:10:48Z

Add support for loading bitstreams on the Altera Cyclone II FPGA populated on the TS-7300 board. This is done through the configuration and data registers offered through a memory interface between the EP93xx SoC and the FPGA via an intermediate CPLD device. The EP93xx SoC on the TS-7300 does not have direct means of configuring the on-board FPGA other than by using the special memory mapped interface to the CPLD. No other entity on the system can control the FPGA bitstream. Signed-off-by: Florian Fainelli Acked-by: Alan Tull Acked-by: Moritz Fischer Signed-off-by: Greg Kroah-Hartman

fpga: Add COMPILE_TEST to all drivers

2016-11-29T21:51:44Z

Like Zynq the Altera drivers compile fine on x86 and others too, so make it easier to compile test this stuff. A10 requires REGMAP_MMIO to compile, so be explicit rather than relying on it via ARCH_SOCFPGA. Signed-off-by: Jason Gunthorpe Acked-by: Alan Tull