kernel.git/drivers/dma/dw/core.c, branch linux-3.16.y

dmaengine: dw: disable BLOCK IRQs for non-cyclic xfer

2016-03-04T10:26:40Z

commit ee1cdcdae59563535485a5f56ee72c894ab7d7ad upstream. The commit 2895b2cad6e7 ("dmaengine: dw: fix cyclic transfer callbacks") re-enabled BLOCK interrupts with regard to make cyclic transfers work. However, this change becomes a regression for non-cyclic transfers as interrupt counters under stress test had been grown enormously (approximately per 4-5 bytes in the UART loop back test). Taking into consideration above enable BLOCK interrupts if and only if channel is programmed to perform cyclic transfer. Fixes: 2895b2cad6e7 ("dmaengine: dw: fix cyclic transfer callbacks") Signed-off-by: Andy Shevchenko Acked-by: Mans Rullgard Tested-by: Mans Rullgard Acked-by: Viresh Kumar Signed-off-by: Vinod Koul Signed-off-by: Luis Henriques

dmaengine: dw: fix cyclic transfer callbacks

2016-02-02T19:09:38Z

commit 2895b2cad6e7a95104cf396e5330054453382ae1 upstream. Cyclic transfer callbacks rely on block completion interrupts which were disabled in commit ff7b05f29fd4 ("dmaengine/dw_dmac: Don't handle block interrupts"). This re-enables block interrupts so the cyclic callbacks can work. Other transfer types are not affected as they set the INT_EN bit only on the last block. Fixes: ff7b05f29fd4 ("dmaengine/dw_dmac: Don't handle block interrupts") Signed-off-by: Mans Rullgard Reviewed-by: Viresh Kumar Signed-off-by: Vinod Koul Signed-off-by: Luis Henriques

dmaengine: dw: fix cyclic transfer setup

2016-02-02T19:09:37Z

commit df3bb8a0e619d501cd13334c3e0586edcdcbc716 upstream. Commit 61e183f83069 ("dmaengine/dw_dmac: Reconfigure interrupt and chan_cfg register on resume") moved some channel initialisation to a new function which must be called before starting a transfer. This updates dw_dma_cyclic_start() to use dwc_dostart() like the other modes, thus ensuring dwc_initialize() gets called and removing some code duplication. Fixes: 61e183f83069 ("dmaengine/dw_dmac: Reconfigure interrupt and chan_cfg register on resume") Signed-off-by: Mans Rullgard Reviewed-by: Viresh Kumar Signed-off-by: Vinod Koul Signed-off-by: Luis Henriques

dmaengine: dw: convert to __ffs()

2015-12-13T17:49:28Z

commit 39416677b95bf1ab8bbfa229ec7e511c96ad5d0c upstream. We replace __fls() by __ffs() since we have to find a *minimum* data width that satisfies both source and destination. While here, rename dwc_fast_fls() to dwc_fast_ffs() which it really is. Fixes: 4c2d56c574db (dw_dmac: introduce dwc_fast_fls()) Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul Signed-off-by: Luis Henriques

dmaengine: dw: properly read DWC_PARAMS register

2015-10-28T10:33:11Z

commit 6bea0f6d1c47b07be88dfd93f013ae05fcb3d8bf upstream. In case we have less than maximum allowed channels (8) and autoconfiguration is enabled the DWC_PARAMS read is wrong because it uses different arithmetic to what is needed for channel priority setup. Re-do the caclulations properly. This now works on AVR32 board well. Fixes: fed2574b3c9f (dw_dmac: introduce software emulation of LLP transfers) Cc: yitian.bu@tangramtek.com Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul Signed-off-by: Luis Henriques

dmaengine: dw: don't perform DMA when dmaengine_submit is called

2014-10-05T20:41:11Z

commit dd8ecfcac66b4485416b2d1df0ec4798b198d7d6 upstream. Accordingly to discussion [1] and followed up documentation the DMA controller driver shouldn't start any DMA operations when dmaengine_submit() is called. This patch fixes the workflow in dw_dmac driver to follow the documentation. [1] http://www.spinics.net/lists/arm-kernel/msg125987.html Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul Cc: "Petallo, MauriceX R" Signed-off-by: Greg Kroah-Hartman

dmaengine: dw: introduce dwc_dostart_first_queued() helper

2014-10-05T20:41:11Z

commit e7637c6c0382485f4d2e20715d058dae6f2b6a7c upstream. We have a duplicate code which starts first descriptor in the queue. Let's make this as a separate helper that can be used in future as well. Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul Cc: "Petallo, MauriceX R" Signed-off-by: Greg Kroah-Hartman

dmaengine: dw: check return code of dma_async_device_register()

2014-05-22T10:07:25Z

dma_async_device_register() may return non-zero error code. In such case we have to follow error path. Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul

dmaengine: dw: fix regression in dw_probe() function

2014-05-22T10:07:24Z

The commit dbde5c29 "dw_dmac: use devm_* functions to simplify code" turns probe function to use devm_* helpers and simultaneously brings a regression. We have to 1) call clk_disable_unprepare() on error path, and 2) check error code of clk_enable_prepare(). First part was done in the original code, second one is an update. Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul

dmaengine: dw: enable clock before access

2014-05-22T10:07:24Z

hclk signal is a bus clock. So, it means we have to have it enabled during access to the DMA controller. This patch makes sure that we enable clock before access to the device, though it currently works on Intel hardware. Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul