<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/crypto/ccp/psp-dev.h, branch linux-6.7.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.7.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.7.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2023-09-15T10:29:46Z</updated>
<entry>
<title>crypto: ccp - Add support for DBC over PSP mailbox</title>
<updated>2023-09-15T10:29:46Z</updated>
<author>
<name>Mario Limonciello</name>
</author>
<published>2023-09-07T18:48:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=0470bb1b71ac1f05055b10bdc791953209a7976b'/>
<id>urn:sha1:0470bb1b71ac1f05055b10bdc791953209a7976b</id>
<content type='text'>
On some SOCs DBC is supported through the PSP mailbox instead of
the platform mailbox. This capability is advertised in the PSP
capabilities register. Allow using this communication path if
supported.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Add support for extended PSP mailbox commands</title>
<updated>2023-09-15T10:29:45Z</updated>
<author>
<name>Mario Limonciello</name>
</author>
<published>2023-09-07T18:48:43Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6e17375c47a325f79e1f80028344bd4b0bdd985b'/>
<id>urn:sha1:6e17375c47a325f79e1f80028344bd4b0bdd985b</id>
<content type='text'>
The PSP mailbox supports a number of extended sub-commands.  These
subcommands are placed in the header of the buffer sent to the mailbox.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Move direct access to some PSP registers out of TEE</title>
<updated>2023-09-15T10:29:45Z</updated>
<author>
<name>Tom Lendacky</name>
</author>
<published>2023-09-07T18:48:42Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=949a0c8dd3c257730ef7205be759e4bc6cf49cea'/>
<id>urn:sha1:949a0c8dd3c257730ef7205be759e4bc6cf49cea</id>
<content type='text'>
With the PSP mailbox registers supporting more than just TEE, access to
them must be maintained and serialized by the PSP device support. Remove
TEE support direct access and create an interface in the PSP support
where the register access can be controlled/serialized.

Signed-off-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Rijo Thomas &lt;Rijo-john.Thomas@amd.com&gt;
Tested-by: Rijo Thomas &lt;Rijo-john.Thomas@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Add support for fetching a nonce for dynamic boost control</title>
<updated>2023-07-20T10:14:21Z</updated>
<author>
<name>Mario Limonciello</name>
</author>
<published>2023-06-23T13:49:55Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c04cf9e14f109ebcc425c1efd2c01294c52a4d62'/>
<id>urn:sha1:c04cf9e14f109ebcc425c1efd2c01294c52a4d62</id>
<content type='text'>
Dynamic Boost Control is a feature offered on AMD client platforms that
allows software to request and set power or frequency limits.

Only software that has authenticated with the PSP can retrieve or set
these limits.

Create a character device and ioctl for fetching the nonce. This ioctl
supports optionally passing authentication information which will influence
how many calls the nonce is valid for.

Acked-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Add support for an interface for platform features</title>
<updated>2023-03-17T03:16:43Z</updated>
<author>
<name>Mario Limonciello</name>
</author>
<published>2023-03-10T21:19:47Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7ccc4f4e2e50e4a29f9ee8f5c9e187f8491bb6e7'/>
<id>urn:sha1:7ccc4f4e2e50e4a29f9ee8f5c9e187f8491bb6e7</id>
<content type='text'>
Some platforms with a PSP support an interface for features that
interact directly with the PSP instead of through a SEV or TEE
environment.

Initialize this interface so that other drivers can consume it.
These drivers may either be subdrivers for the ccp module or
external modules.  For external modules, export a symbol for them
to utilize.

Acked-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Move some PSP mailbox bit definitions into common header</title>
<updated>2023-03-17T03:16:43Z</updated>
<author>
<name>Mario Limonciello</name>
</author>
<published>2023-03-10T21:19:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1c5c1daf04d13916867ef68c6ba7ae4f5e73801f'/>
<id>urn:sha1:1c5c1daf04d13916867ef68c6ba7ae4f5e73801f</id>
<content type='text'>
Some of the bits and fields used for mailboxes communicating with the
PSP are common across all mailbox implementations (SEV, TEE, etc).

Move these bits into the common `linux/psp.h` so they don't need to
be re-defined for each implementation.

Acked-by: Rijo Thomas &lt;Rijo-john.Thomas@amd.com&gt;
Acked-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Acked-by: Jarkko Nikula &lt;jarkko.nikula@linux.intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Drop TEE support for IRQ handler</title>
<updated>2023-03-17T03:16:43Z</updated>
<author>
<name>Mario Limonciello</name>
</author>
<published>2023-03-10T21:19:44Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a7ca7bbdb59e59a7890116e03a3bb99bcf4c87a6'/>
<id>urn:sha1:a7ca7bbdb59e59a7890116e03a3bb99bcf4c87a6</id>
<content type='text'>
The only PSP mailbox that currently supports interrupt on completion
is the SEV mailbox.  Drop the dead code for the TEE subdriver to
potentially call it.

Acked-by: Rijo Thomas &lt;Rijo-john.Thomas@amd.com&gt;
Acked-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Export PSP security bits to userspace</title>
<updated>2022-04-08T08:26:43Z</updated>
<author>
<name>Mario Limonciello</name>
</author>
<published>2022-03-31T21:12:11Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=50c4decc1b15313afa31f9a99da0904fa9c9b071'/>
<id>urn:sha1:50c4decc1b15313afa31f9a99da0904fa9c9b071</id>
<content type='text'>
The PSP sets several pre-defined bits in the capabilities
register to indicate that security attributes of the platform.

Export these attributes into userspace for administrators to
confirm platform is properly locked down.

Acked-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - cache capability into psp device</title>
<updated>2022-04-08T08:25:19Z</updated>
<author>
<name>Mario Limonciello</name>
</author>
<published>2022-03-31T21:12:10Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cac32cd4f1436b0f926a9112039d3f7ce1cd6cab'/>
<id>urn:sha1:cac32cd4f1436b0f926a9112039d3f7ce1cd6cab</id>
<content type='text'>
The results of the capability register will be used by future
code at runtime rather than just initialization.

Acked-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - add TEE support for Raven Ridge</title>
<updated>2019-12-20T06:58:32Z</updated>
<author>
<name>Rijo Thomas</name>
</author>
<published>2019-12-04T06:19:02Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=33960acccfbd7f24d443cb3d0312ac28abe62bae'/>
<id>urn:sha1:33960acccfbd7f24d443cb3d0312ac28abe62bae</id>
<content type='text'>
Adds a PCI device entry for Raven Ridge. Raven Ridge is an APU with a
dedicated AMD Secure Processor having Trusted Execution Environment (TEE)
support. The TEE provides a secure environment for running Trusted
Applications (TAs) which implement security-sensitive parts of a feature.

This patch configures AMD Secure Processor's TEE interface by initializing
a ring buffer (shared memory between Rich OS and Trusted OS) which can hold
multiple command buffer entries. The TEE interface is facilitated by a set
of CPU to PSP mailbox registers.

The next patch will address how commands are submitted to the ring buffer.

Cc: Jens Wiklander &lt;jens.wiklander@linaro.org&gt;
Cc: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Cc: Ard Biesheuvel &lt;ard.biesheuvel@linaro.org&gt;
Co-developed-by: Devaraj Rangasamy &lt;Devaraj.Rangasamy@amd.com&gt;
Signed-off-by: Devaraj Rangasamy &lt;Devaraj.Rangasamy@amd.com&gt;
Signed-off-by: Rijo Thomas &lt;Rijo-john.Thomas@amd.com&gt;
Acked-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
</feed>
