<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/crypto/ccp/ccp-dev-v3.c, branch linux-4.12.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.12.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.12.y'/>
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<updated>2017-04-24T10:11:06Z</updated>
<entry>
<title>crypto: ccp - Change ISR handler method for a v3 CCP</title>
<updated>2017-04-24T10:11:06Z</updated>
<author>
<name>Gary R Hook</name>
</author>
<published>2017-04-21T15:50:05Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7b537b24e76a1e8e6d7ea91483a45d5b1426809b'/>
<id>urn:sha1:7b537b24e76a1e8e6d7ea91483a45d5b1426809b</id>
<content type='text'>
The CCP has the ability to perform several operations simultaneously,
but only one interrupt.  When implemented as a PCI device and using
MSI-X/MSI interrupts, use a tasklet model to service interrupts. By
disabling and enabling interrupts from the CCP, coupled with the
queuing that tasklets provide, we can ensure that all events
(occurring on the device) are recognized and serviced.

This change fixes a problem wherein 2 or more busy queues can cause
notification bits to change state while a (CCP) interrupt is being
serviced, but after the queue state has been evaluated. This results
in the event being 'lost' and the queue hanging, waiting to be
serviced. Since the status bits are never fully de-asserted, the
CCP never generates another interrupt (all bits zero -&gt; one or more
bits one), and no further CCP operations will be executed.

Cc: &lt;stable@vger.kernel.org&gt; # 4.9.x+

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Enable 3DES function on v5 CCPs</title>
<updated>2017-03-24T14:02:55Z</updated>
<author>
<name>Gary R Hook</name>
</author>
<published>2017-03-15T18:20:52Z</published>
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<id>urn:sha1:990672d48515ce09c76fcf1ceccee48b0dd1942b</id>
<content type='text'>
Wire up support for Triple DES in ECB mode.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Clean up the LSB slot allocation code</title>
<updated>2016-10-25T03:08:23Z</updated>
<author>
<name>Gary R Hook</name>
</author>
<published>2016-10-18T22:33:37Z</published>
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<id>urn:sha1:103600ab966a2f02d8986bbfdf87b762b1c6a06d</id>
<content type='text'>
Fix a few problems revealed by testing: verify consistent
units, especially in public slot allocation. Percolate
some common initialization code up to a common routine.
Add some comments.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Make syslog errors human-readable</title>
<updated>2016-10-02T14:33:45Z</updated>
<author>
<name>Gary R Hook</name>
</author>
<published>2016-09-28T16:53:56Z</published>
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<id>urn:sha1:81422badb39078fde1ffcecda3caac555226fc7b</id>
<content type='text'>
Add human-readable strings to log messages about CCP errors

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - clean up data structure</title>
<updated>2016-10-02T14:33:44Z</updated>
<author>
<name>Gary R Hook</name>
</author>
<published>2016-09-28T16:53:47Z</published>
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<id>urn:sha1:9ddb9dc6be095ebe393f7eb582df09cc4847c5e9</id>
<content type='text'>
Change names of data structure instances.  Add const
keyword where appropriate.  Add error handling path.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Add support for the RNG in a version 5 CCP</title>
<updated>2016-08-09T10:47:17Z</updated>
<author>
<name>Gary R Hook</name>
</author>
<published>2016-07-27T00:10:31Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=084935b208f6507ef5214fd67052a67a700bc6cf'/>
<id>urn:sha1:084935b208f6507ef5214fd67052a67a700bc6cf</id>
<content type='text'>
Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Let a v5 CCP provide the same function as v3</title>
<updated>2016-08-09T10:47:16Z</updated>
<author>
<name>Gary R Hook</name>
</author>
<published>2016-07-27T00:10:21Z</published>
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<id>urn:sha1:4b394a232df78414442778b02ca4a388d947d059</id>
<content type='text'>
Enable equivalent function on a v5 CCP. Add support for a
version 5 CCP which enables AES/XTS/SHA services. Also,
more work on the data structures to virtualize
functionality.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Refactor code to enable checks for queue space.</title>
<updated>2016-08-09T10:47:10Z</updated>
<author>
<name>Gary R Hook</name>
</author>
<published>2016-07-27T00:10:13Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=bb4e89b34d1bf46156b7e880a0f34205fb7ce2a5'/>
<id>urn:sha1:bb4e89b34d1bf46156b7e880a0f34205fb7ce2a5</id>
<content type='text'>
Available queue space is used to decide (by counting free slots)
if we have to put a command on hold or if it can be sent
to the engine immediately.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Refactor code supporting the CCP's RNG</title>
<updated>2016-08-09T10:47:09Z</updated>
<author>
<name>Gary R Hook</name>
</author>
<published>2016-07-27T00:10:02Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8256e683113e659d9bf6bffdd227eeb1881ae9a7'/>
<id>urn:sha1:8256e683113e659d9bf6bffdd227eeb1881ae9a7</id>
<content type='text'>
Make the RNG support code common (where possible) in
preparation for adding a v5 device.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Refactor the storage block allocation code</title>
<updated>2016-08-09T10:47:08Z</updated>
<author>
<name>Gary R Hook</name>
</author>
<published>2016-07-27T00:09:50Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=58a690b701efc32ffd49722dd7b887154eb5a205'/>
<id>urn:sha1:58a690b701efc32ffd49722dd7b887154eb5a205</id>
<content type='text'>
Move the KSB access/management functions to the v3
device file, and add function pointers to the actions
structure. At the operations layer all of the references
to the storage block will be generic (virtual). This is
in preparation for a version 5 device, in which the
private storage block is managed differently.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
</feed>
