kernel.git/drivers/clk/x86, branch linux-4.16.y

clk: x86: Do not gate clocks enabled by the firmware

2017-07-18T23:23:13Z

Read the enable register to determine if the clock is already in use by the firmware. In this case avoid gating the clock. Tested-by: Enric Balletbo i Serra Acked-by: Andy Shevchenko Acked-by: Darren Hart (VMware) Signed-off-by: Carlo Caione Fixes: 282a4e4ce5f9 ("platform/x86: Enable Atom PMC platform clocks") Signed-off-by: Stephen Boyd

clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL

2017-05-01T18:13:25Z

clkdev_hw_create() returns NULLs on error, it doesn't return error pointers. Fixes: 41ee7caf59e1 ("clk: x86: add "mclk" alias for Baytrail/Cherrytrail") Signed-off-by: Dan Carpenter Acked-by: Pierre-Louis Bossart Signed-off-by: Stephen Boyd

clk: x86: add "mclk" alias for Baytrail/Cherrytrail

2017-04-19T16:52:32Z

Due to timing requirements, TI and Conexant manage the audio reference clock from their ASoC codec drivers using the "mclk" string. This patch adds another lookup for the "pmc_plt_clk_3" clock to avoid Intel-specific tests in those codec drivers and use code as-is. To avoid a leak, clk_add_alias() is not used in this patch. Instead the lookup is created manually as part of the .probe() step and dropped in the .remove() step. "pmc_plt_clk_3" is used exclusively for audio on all known Baytrail/CherryTrail designs and is e.g. routed on the MCLK (pin 26) of the MinnowBoardMAX Turbot LSE connector. Signed-off-by: Pierre-Louis Bossart Signed-off-by: Stephen Boyd

clk: x86: Add Atom PMC platform clocks

2017-01-27T00:20:46Z

The BayTrail and CherryTrail platforms provide platform clocks through their Power Management Controller (PMC). The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks are available for general system use, where appropriate, and each have Control & Frequency register fields associated with them. Port from legacy by Pierre Bossart, integration in clock framework by Irina Tirdea Signed-off-by: Irina Tirdea Signed-off-by: Pierre-Louis Bossart Acked-by: Andy Shevchenko Signed-off-by: Stephen Boyd

clk: x86: Remove clkdev.h and clk.h includes

2016-03-03T19:27:26Z

This driver is a clk provider and not a clk consumer, so remove the clk.h include. Also, drop clkdev.h because there's not clkdev usage here either. Acked-by: Mika Westerberg Signed-off-by: Stephen Boyd

clk: x86: Remove CLK_IS_ROOT

2016-03-03T19:27:18Z

This flag is a no-op now. Remove usage of the flag. Acked-by: Mika Westerberg Signed-off-by: Stephen Boyd

clk: x86: drop owner assignment from platform_drivers

2014-10-20T14:20:23Z

A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang

ACPI / LPSS: add support for Intel BayTrail

2013-06-18T23:08:47Z

Intel BayTrail has almost the same Low Power Subsystem than Lynxpoint with few differences. Peripherals are clocked with different speeds (typically lower) and the clock is not always gated. To support this we add possibility to share a common fixed rate clock and make clock gating optional. Signed-off-by: Mika Westerberg Acked-by: Mike Turquette Signed-off-by: Rafael J. Wysocki

ACPI / LPSS: register clock device for Lynxpoint DMA properly

2013-05-14T04:53:58Z

The DMA controller in Lynxpoint is enumerated as a regular ACPI device now. To work properly it is using the LPSS root clock as a functional clock. That's why we have to register the clock device accordingly to the ACPI ID of the DMA controller. The acpi_lpss.c module is responsible to do the job. This patch also removes hardcoded name of the DMA device in clk-lpt.c and the name of the root clock in acpi_lpss.c. Signed-off-by: Rafael J. Wysocki Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul

ACPI / scan: Add special handler for Intel Lynxpoint LPSS devices

2013-03-21T21:44:38Z

Devices on the Intel Lynxpoint Low Power Subsystem (LPSS) have some common features that aren't shared with any other platform devices, including the clock and LTR (Latency Tolerance Reporting) registers. It is better to handle those features in common code than to bother device drivers with doing that (I/O functionality-wise the LPSS devices are generally compatible with other devices that don't have those special registers and may be handled by the same drivers). The clock registers of the LPSS devices are now taken care of by the special clk-x86-lpss driver, but the MMIO mappings used for accessing those registers can also be used for accessing the LTR registers on those devices (LTR support for the Lynxpoint LPSS is going to be added by a subsequent patch). Thus it is convenient to add a special ACPI scan handler for the Lynxpoint LPSS devices that will create the MMIO mappings for accessing the clock (and LTR in the future) registers and will register the LPSS devices' clocks, so the clk-x86-lpss driver will only need to take care of the main Lynxpoint LPSS clock. Introduce a special ACPI scan handler for Intel Lynxpoint LPSS devices as described above. This also reduces overhead related to browsing the ACPI namespace in search of the LPSS devices before the registration of their clocks, removes some LPSS-specific (and somewhat ugly) code from acpi_platform.c and shrinks the overall code size slightly. Signed-off-by: Mika Westerberg Signed-off-by: Rafael J. Wysocki Acked-by: Mike Turquette