kernel.git/drivers/clk/uniphier, branch linux-5.0.y

clk: uniphier: Fix update register for CPU-gear

2019-03-23T19:11:28Z

commit 521282237b9d78b9bff423ec818becd4c95841c2 upstream. Need to set the update bit in UNIPHIER_CLK_CPUGEAR_UPD to update the CPU-gear value. Fixes: d08f1f0d596c ("clk: uniphier: add CPU-gear change (cpufreq) support") Cc: linux-stable@vger.kernel.org Signed-off-by: Kunihiko Hayashi Acked-by: Masahiro Yamada Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: uniphier: add clock frequency support for SPI

2018-07-25T23:26:18Z

Add clock control for SPI controller on UniPhier SoCs. Signed-off-by: Kunihiko Hayashi Signed-off-by: Masahiro Yamada Signed-off-by: Stephen Boyd

clk: uniphier: add more USB3 PHY clocks

2018-07-25T22:45:32Z

Add USB3 PHY clocks where missing. Use fixed-factor clocks for those without gating. For clarification, prefix clock names with 'ss' or 'hs'. Signed-off-by: Masahiro Yamada Signed-off-by: Stephen Boyd

clk: uniphier: add NAND 200MHz clock

2018-07-25T22:45:25Z

The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada Signed-off-by: Stephen Boyd

clk: uniphier: add LD11/LD20 stream demux system clock

2018-05-15T21:15:43Z

Add clock for MPEG2 transport stream I/O and demux system (HSC) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki Acked-by: Masahiro Yamada Signed-off-by: Stephen Boyd

clk: uniphier: add additional ethernet clock lines for Pro4

2018-04-05T22:03:51Z

Pro4 SoC has clock lines for Giga-bit feature and ethernet phy, and these are mandatory to activate the ethernet controller. This adds support for the clock lines. Signed-off-by: Kunihiko Hayashi Acked-by: Masahiro Yamada Signed-off-by: Stephen Boyd

clk: uniphier: add SATA clock control support

2018-04-05T22:03:49Z

Add clock control for SATA controller on UniPhier SoCs. This adds support for PXs2, LD20 and PXs3. Signed-off-by: Kunihiko Hayashi Acked-by: Masahiro Yamada Signed-off-by: Stephen Boyd

clk: uniphier: add PCIe clock control support

2018-04-05T22:03:45Z

Add clock control for PCIe controller on UniPhier SoCs. This adds support for Pro5, LD20 and PXs3. Signed-off-by: Kunihiko Hayashi Acked-by: Masahiro Yamada Signed-off-by: Stephen Boyd

clk: uniphier: add ethernet clock control support for PXs3

2018-03-23T16:39:36Z

Add clock control for ethernet controller on PXs3 SoC. Signed-off-by: Kunihiko Hayashi Acked-by: Masahiro Yamada Signed-off-by: Stephen Boyd

clk: uniphier: add Pro4/Pro5/PXs2 audio system clock

2018-03-19T20:42:49Z

Add clock for audio subsystem (AIO) on UniPhier Pro4/Pro5/PXs2 SoCs. Signed-off-by: Katsuhiro Suzuki Acked-by: Masahiro Yamada Signed-off-by: Stephen Boyd