kernel.git/drivers/clk/sunxi/Makefile, branch linux-4.4.y

clk: sunxi: mod1 clock support

2015-10-21T19:51:29Z

The module 1 type of clocks consist of a gate and a mux and are used on the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or SPDIF. This commit adds support for them on the sunxi clock driver. Signed-off-by: Emilio López Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai

clk: sunxi: codec clock support

2015-10-21T19:51:28Z

The codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as parent. Add a driver for such a clock. Signed-off-by: Emilio López Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai

clk: sunxi: Add a driver for the PLL2

2015-10-21T19:51:27Z

The PLL2 on the A10 and later SoCs is the clock used for all the audio related operations. This clock has a somewhat complex output tree, with three outputs (2X, 4X and 8X) with a fixed divider from the base clock, and an output (1X) with a post divider. However, we can simplify things since the 1X divider can be fixed, and we end up by having a base clock not exposed to any device (or at least directly, since the 4X output doesn't have any divider), and 4 fixed divider clocks that will be exposed. This clock seems to have been introduced, at least in this form, in the revision B of the A10, but we don't have any information on the clock used on the revision A. Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai

clk: sunxi: Add a simple gates driver

2015-08-12T07:59:15Z

The gates were handled with a common piece of framework that was registering all gates array, that was not using the CLK_OF_DECLARE logic, and was not using clock-indices but some private masks that were pretty much equivalent. Move this code in a new driver that handles all the gates array and solves both these issues. Signed-off-by: Maxime Ripard Signed-off-by: Michael Turquette [sboyd@codeaurora.org: Include clk.h for consumer API usage] Signed-off-by: Stephen Boyd

clk: sunxi: Move USB clocks to separate file

2015-02-23T08:25:54Z

The USB clocks originally shared code with the gates clocks, but had additional reset controllers. Move these to a separate file. This will allow us to add new support for slightly different USB clocks, such as on the A80, without affecting gates clocks, and also facilitate the migration of gates clocks to a generic solution. This also cleans up the USB clocks code slightly, such as adding newlines, getting rid of the unused clkdev call, using a simple u32 instead of BITMAP for the clock masks, using BIT() macro to declare the clock bitmasks, and using of_io_request_and_map() to get the I/O address. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard

clk: sunxi: Add driver for A80 MMC config clocks/resets

2015-01-20T16:14:38Z

On the A80 SoC, the 4 mmc controllers each have a separate register controlling their register access clocks and reset controls. These registers in turn share a ahb clock gate and reset control. This patch adds a platform device driver for these controls. It requires both clocks and reset controls to be available, so using CLK_OF_DECLARE might not be the best way. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard

clk: sunxi: Add support for A80 basic bus clocks

2014-10-21T19:45:48Z

The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a new "GT" bus, which I assume is some kind of data bus connecting the processor cores, memory and various busses. Also there is a bus clock for a ARM CCI400 module. As far as I can tell, the GT bus and CCI400 bus clock must be protected. This patch adds driver support for peripheral related PLLs and bus clocks on the A80. The GT and CCI400 clocks are added as well as these 2 along with the PLLs they are clocked from must not be disabled. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard

clk: sunxi: Add sun8i MBUS clock support

2014-09-27T07:05:43Z

The MBUS clock on sun8i is slightly different from the old mod0 clocks. The divider is 3 bits wider, while also needing a divider table for the higher 4 values, which all set the same divider. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard

clk: sunxi: Move mod0 clock to a file of its own

2014-09-27T06:58:03Z

Since we know have the ability to declare factors clock outside of clk-sunxi, create a new mod0 driver to deal with the mod0 clocks. Signed-off-by: Maxime Ripard Acked-by: Hans de Goede

clk: sunxi: Add A23 APB0 divider clock support

2014-07-07T08:46:21Z

The A23 has an almost identical PRCM clock tree. The difference in the APB0 clock is the smallest divisor is 1, instead of 2. This patch adds a separate sun8i-a23-apb0-clk driver to support it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard