kernel.git/drivers/clk/st/Makefile, branch linux-3.15.y

clk: st: Support for QUADFS inside ClockGenB/C/D/E/F

2014-03-25T22:59:09Z

The patch supports the 216/432/660 type Quad Frequency Synthesizers used by ClockGenB/C/D/E/F QUADFS clock : It includes support for all 216/432/660 type Quad Frequency Synthesizers : implemented as Fixed Parent / Rate / Gate clock, with clock rate calculated reading H/w settings done at BOOT. QuadFS have 4 outputs : chan0 chan1 chan2 chan3 Signed-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez Signed-off-by: Mike Turquette

clk: st: Support for PLLs inside ClockGenA(s)

2014-03-25T22:58:56Z

The patch supports the c65/c32 type PLLs used by ClockGenA(s) PLL clock : It includes support for all c65/c32 type PLLs inside ClockGenA(s) : implemented as Fixed Parent / Fixed Rate clock, with clock rate calculated reading H/w settings done at BOOT. c65 PLLs have 2 outputs : HS and LS c32 PLLs have 1-4 outputs : ODFx Signed-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez Signed-off-by: Mike Turquette

clk: st: Support for DIVMUX and PreDiv Clocks

2014-03-25T22:58:47Z

The patch supports the DIVMUX and PreDiv clocks used by ClockGenA(s) DIVMUX clock : Divider-Multiplexer-Gate inside ClockGenA(s) It includes support for each channel : 3-parent Multiplexer, Divider for each Parent, Gate to switch OFF the output channel. The clock is implemented using generic clocks implemented in the kernel clk_divider and clk_mux. PreDiv clock : Fixed Divider Clock used inside ClockGenA(s) to divide the oscillator clock by factor-of-16. The clock is implemented using generic clocks implemented in the kernel clk_divider. Signed-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez Signed-off-by: Mike Turquette