kernel.git/drivers/clk/rockchip, branch linux-6.10.y

clk: rockchip: fix error for unknown clocks

2024-10-10T10:00:59Z

commit 12fd64babaca4dc09d072f63eda76ba44119816a upstream. There is a clk == NULL check after the switch to check for unsupported clk types. Since clk is re-assigned in a loop, this check is useless right now for anything but the first round. Let's fix this up by assigning clk = NULL in the loop before the switch statement. Fixes: a245fecbb806 ("clk: rockchip: add basic infrastructure for clock branches") Cc: stable@vger.kernel.org Signed-off-by: Sebastian Reichel [added fixes + stable-cc] Link: https://lore.kernel.org/r/20240325193609.237182-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p

2024-10-04T14:33:09Z

[ Upstream commit 0d02e8d284a45bfa8997ebe8764437b8eb6b108b ] The 32kHz input clock is named "xin32k" in the driver, so the name "32k" appears to be a typo in this case. Lets fix this. Signed-off-by: Alexander Shiyan Reviewed-by: Dragan Simic Fixes: f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Link: https://lore.kernel.org/r/20240829052820.3604-1-eagle.alexander923@gmail.com Signed-off-by: Heiko Stuebner Signed-off-by: Sasha Levin

clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228

2024-10-04T14:33:03Z

[ Upstream commit 1d34b9757523c1ad547bd6d040381f62d74a3189 ] Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically parented by the hdmiphy clk and it is expected that the DCLK_VOP and hdmiphy clk rate are kept in sync. Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used on RK3328, to make full use of all possible supported display modes. Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP") Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228") Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240615170417.3134517-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner Signed-off-by: Sasha Levin

clk: rockchip: rk3568: Add PLL rate for 724 MHz

2024-05-04T10:38:13Z

This rate allows to provide a low-jitter 72,4 MHz pixelclock for a custom eDP panel from the VPLL. Signed-off-by: Lucas Stach Link: https://lore.kernel.org/r/20240503153329.3906030-1-l.stach@pengutronix.de Signed-off-by: Heiko Stuebner

clk: rockchip: Remove an unused field in struct rockchip_mmc_clock

2024-05-04T10:38:02Z

In "struct rockchip_mmc_clock", the 'id' field is unused. Remove it. Found with cppcheck, unusedStructMember. Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/410bc0f86c7b9f1c80f8a4e9a2a028a9a6ee1ec0.1713970085.git.christophe.jaillet@wanadoo.fr Signed-off-by: Heiko Stuebner

clk: rockchip: rk3588: Add reset line for HDMI Receiver

2024-04-10T05:10:40Z

Export hdmirx_biu reset line required by the Synopsys DesignWare HDMIRX Controller. Signed-off-by: Shreeya Patel Link: https://lore.kernel.org/r/20240327225057.672304-3-shreeya.patel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: rk3568: Add missing USB480M_PHY mux

2024-04-10T05:10:17Z

The USB480M clock can source from a MUX that selects the clock to come from either of the USB-phy internal 480MHz PLLs. These clocks are provided by the USB phy driver. Signed-off-by: David Jander Link: https://lore.kernel.org/r/20240404-clk-rockchip-rk3568-add-usb480m-phy-mux-v1-1-e8542afd58b9@pengutronix.de Signed-off-by: Sascha Hauer Link: https://lore.kernel.org/r/20240405-clk-rk3568-usb480m-phy-mux-v1-2-6c89de20a6ff@pengutronix.de Signed-off-by: Heiko Stuebner

clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent

2024-02-27T22:45:53Z

Otherwise when when clk_i2s0 muxes to clk_i2s0_div which requires setting high divider value on clk_i2s0_div, and then muxes back to clk_i2s0_frac, clk_i2s0_frac would have no way to change the clk_i2s0_div's divider ratio back to 1 so that it can satisfy the condition for m/n > 20 for fractional division to work correctly. Bug is reproducible by playing 44.1k audio, then 48k audio, and then 44.1k audio again. This results in clk_i2s0_div being set to 49 and clk_i2s0_frac not being able to cope with such a low input clock rate and audio playing extremely slowly. The identical issue is on i2s1 and i2s2 clocks, too. Signed-off-by: Ondrej Jirman Link: https://lore.kernel.org/r/20240217193439.1762213-1-megi@xff.cz Signed-off-by: Heiko Stuebner

clk: rockchip: rk3588: use linked clock ID for GATE_LINK

2024-02-27T21:23:06Z

In preparation for properly supporting GATE_LINK switch the unused linked clock argument from the clock's name to its ID. This allows easy and fast lookup of the 'struct clk'. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240126182919.48402-7-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: rk3588: fix indent

2024-02-27T21:23:06Z

pclk_mailbox2 is the only RK3588 clock indented with one tab instead of two tabs. Let's fix this. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240126182919.48402-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner