kernel.git/drivers/clk/rockchip/Makefile, branch linux-4.5.y

clk: rockchip: add clock controller for rk3228

2015-12-12T19:04:54Z

Add the clock tree definition for the new rk3228 SoC. Signed-off-by: Jeffy Chen Signed-off-by: Heiko Stuebner

clk: rockchip: add clock controller for rk3036

2015-11-23T20:59:19Z

Add the clock tree definition for the new rk3036 SoC. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner

clk: rockchip: add rk3368 clock controller

2015-07-06T22:09:22Z

Describe the clock tree and software resets of the rk3368 ARM64 SoC Signed-off-by: Heiko Stuebner Signed-off-by: Stephen Boyd

clk: rockchip: add support for phase inverters

2015-07-06T22:04:40Z

Most Rockchip socs have optional phase inverters connected to some clocks that move the clock-phase by 180 degrees. Signed-off-by: Heiko Stuebner [sboyd@codeaurora.org: Dropped lazy part of commit text] Signed-off-by: Stephen Boyd

clk: rockchip: Add support for the mmc clock phases using the framework

2014-11-27T23:44:24Z

This patch adds the 2 physical clocks for the mmc (drive and sample). They're mostly there for the phase properties, but they also show the true clock (by dividing by RK3288_MMC_CLKGEN_DIV). The drive and sample phases are generated by dividing an upstream parent clock by 2, this allows us to adjust the phase by 90 deg. There's also an option to have up to 255 delay elements (40-80 picoseconds long). This driver uses those elements (under the assumption that they're 60 ps long) to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as 90 deg if the delay elements are as big as 80 ps, so a finer division (smaller than 22.5) was not picked because the phase might not be monotonic anymore. Suggested-by: Heiko Stuebner Signed-off-by: Alexandru M Stan Signed-off-by: Heiko Stuebner

clk: rockchip: add new clock-type for the cpuclk

2014-09-27T15:57:41Z

When changing the armclk on Rockchip SoCs it is supposed to be reparented to an alternate parent before changing the underlying pll and back after the change. Additionally there exist clocks that are very tightly bound to the armclk whose divider values are set according to the armclk rate. Add a special clock-type to handle all that. The rate table and divider values will be supplied from the soc-specific clock controllers. Signed-off-by: Heiko Stuebner Reviewed-by: Doug Anderson On a rk3288-board: Tested-by: Doug Anderson

clk: rockchip: add clock controller for rk3288

2014-07-13T19:17:10Z

Add the clock tree definition for the new rk3288 SoC. Signed-off-by: Heiko Stuebner Acked-By: Max Schwarz Tested-By: Max Schwarz Signed-off-by: Mike Turquette

clk: rockchip: add clock driver for rk3188 and rk3066 clocks

2014-07-13T19:17:09Z

This adds a clock driver that handles the specific muxes, dividers and gates of rk3188 and rk3066 SoCs. The structure of the clock list resembles the arrangement of their counterparts in the clock architecture diagrams found in the SoC documentation. Clocks exported to the clock provider are currently limited to well known or measured ones. So additional clock exports may be necessary in the future. Signed-off-by: Heiko Stuebner Acked-By: Max Schwarz Tested-By: Max Schwarz Signed-off-by: Mike Turquette

clk: rockchip: add reset controller

2014-07-13T19:17:07Z

All Rockchip SoCs at least down to the ARM9-based RK28xx include the reset- controller for SoC peripherals in their clock controller. While the older SoCs (ARM9 and Cortex-A8) use a regular scheme to change register values, the Cortex-A9 SoCs use a hiword-mask making locking unecessary. To be compatible with both schemes the reset controller takes a flag to decide which scheme to use, similar to the other HIWORD_MASK flags used in the clock framework. Signed-off-by: Heiko Stuebner Acked-By: Max Schwarz Tested-By: Max Schwarz Signed-off-by: Mike Turquette

clk: rockchip: add clock type for pll clocks and pll used on rk3066

2014-07-13T19:17:06Z

All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: Heiko Stuebner Acked-By: Max Schwarz Tested-By: Max Schwarz Signed-off-by: Mike Turquette