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<title>kernel.git/drivers/clk/qcom/common.c, branch linux-4.4.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.4.y</id>
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<updated>2020-01-04T12:34:30Z</updated>
<entry>
<title>clk: qcom: Allow constant ratio freq tables for rcg</title>
<updated>2020-01-04T12:34:30Z</updated>
<author>
<name>Jeffrey Hugo</name>
</author>
<published>2019-10-31T18:57:15Z</published>
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<id>urn:sha1:4127a30af64af0fb93272b1b39fe08579bae6b31</id>
<content type='text'>
[ Upstream commit efd164b5520afd6fb2883b68e0d408a7de29c491 ]

Some RCGs (the gfx_3d_src_clk in msm8998 for example) are basically just
some constant ratio from the input across the entire frequency range.  It
would be great if we could specify the frequency table as a single entry
constant ratio instead of a long list, ie:

	{ .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 },
        { }

So, lets support that.

We need to fix a corner case in qcom_find_freq() where if the freq table
is non-null, but has no frequencies, we end up returning an "entry" before
the table array, which is bad.  Then, we need ignore the freq from the
table, and instead base everything on the requested freq.

Suggested-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Jeffrey Hugo &lt;jeffrey.l.hugo@gmail.com&gt;
Link: https://lkml.kernel.org/r/20191031185715.15504-1-jeffrey.l.hugo@gmail.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Drop calls to qcom_cc_remove()</title>
<updated>2015-10-09T06:53:01Z</updated>
<author>
<name>Stephen Boyd</name>
</author>
<published>2015-10-08T07:11:49Z</published>
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<id>urn:sha1:9bc432cb242b0edff81e3ab83ba11c327cd4dd93</id>
<content type='text'>
Now that qcom_cc_remove() is a nop, drop calls to
qcom_cc_remove() and any empty driver remove functions.

Cc: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>qcom: clk: Make qcom_cc_probe() fully devm safe</title>
<updated>2015-10-09T06:53:00Z</updated>
<author>
<name>Stephen Boyd</name>
</author>
<published>2015-10-08T06:59:57Z</published>
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<id>urn:sha1:94c51f4073260e775fa404a45ac7f7adea590d0a</id>
<content type='text'>
Some APIs in qcom_cc_probe() don't have a devm counterpart, so we
have to use the calling device's platform data to pass pointers
to the remove path. Let's use devm_add_action() instead, so that
the remove path doesn't need to do anything, allowing us to
remove qcom_cc_remove() entirely.

Cc: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: gdsc: Add support for ON only state</title>
<updated>2015-09-16T22:22:40Z</updated>
<author>
<name>Rajendra Nayak</name>
</author>
<published>2015-08-06T10:37:45Z</published>
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<id>urn:sha1:3c53f5e2179874441a1741ec7bcbaa92fcec9c79</id>
<content type='text'>
Certain devices can have GDSCs' which support ON as the only state.
They can't be power collapsed to either hit RET or OFF.
The clients drivers for these GDSCs' however would expect the state
of the core to be reset following a GDSC disable and re-enable.
To do this assert/deassert reset lines every time the client
driver would request the GDSC to be powered on/off instead.

Signed-off-by: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: gdsc: Prepare common clk probe to register gdscs</title>
<updated>2015-09-16T22:22:37Z</updated>
<author>
<name>Rajendra Nayak</name>
</author>
<published>2015-08-06T10:37:43Z</published>
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<id>urn:sha1:5e5cc241e9c448d1f6e5fdef843ab018a9947d5c</id>
<content type='text'>
The common clk probe registers a clk provider and a reset controller.
Update it to register a genpd provider using the gdsc data provided
by each platform.

Signed-off-by: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()</title>
<updated>2015-08-24T23:48:43Z</updated>
<author>
<name>Stephen Boyd</name>
</author>
<published>2015-06-25T23:53:23Z</published>
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<id>urn:sha1:497295afb5ab070211a9963c80a89bc6fbfd6197</id>
<content type='text'>
Mostly converted with the following semantic patch:

@@
struct clk_hw *E;
@@

-__clk_get_num_parents(E-&gt;clk)
+clk_hw_get_num_parents(E)

Acked-by: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Cc: Chao Xie &lt;chao.xie@marvell.com&gt;
Cc: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
Cc: Javier Martinez Canillas &lt;javier.martinez@collabora.co.uk&gt;
Cc: Tomasz Figa &lt;tomasz.figa@gmail.com&gt;
Cc: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Cc: "Emilio López" &lt;emilio@elopez.com.ar&gt;
Acked-by: Tero Kristo &lt;t-kristo@ti.com&gt;
Cc: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Acked-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Give clk-qcom.ko module a GPLv2 license</title>
<updated>2015-07-28T18:59:26Z</updated>
<author>
<name>Stephen Boyd</name>
</author>
<published>2015-07-24T18:55:42Z</published>
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<id>urn:sha1:169f05e80522e2848c9089a17976ebf31e735d5c</id>
<content type='text'>
The missing license causes the clk-qcom.ko module to taint the
kernel. Add the appropriate license to avoid taint.

Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Introduce parent_map tables</title>
<updated>2015-03-23T23:09:19Z</updated>
<author>
<name>Georgi Djakov</name>
</author>
<published>2015-03-20T16:30:26Z</published>
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<id>urn:sha1:293d2e97b37f545bb36aef78cd549d9e6cd66e7f</id>
<content type='text'>
In the current parent mapping code, we can get duplicate or inconsistent
indexes, which leads to discrepancy between the number of elements in the
array and the number of parents. Until now, this was solved with some
reordering but this is not always possible.

This patch introduces index tables that are used to define the relations
between the PLL source and the hardware mux configuration value.
To accomplish this, here we do the following:
 - Define a parent_map struct to map the relations between PLL source index
 and register configuration value.
 - Add a qcom_find_src_index() function for finding the index of a clock
 matching the specific PLL configuration.
 - Update the {set,get}_parent RCG functions use the newly introduced
 parent_map struct.
 - Convert all existing drivers to the new parent_map tables.

Signed-off-by: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Consolidate frequency finding logic</title>
<updated>2014-09-22T22:16:52Z</updated>
<author>
<name>Stephen Boyd</name>
</author>
<published>2014-09-04T20:21:50Z</published>
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<id>urn:sha1:50c6a50344c58f73c697e2fe38960dc176a2e69f</id>
<content type='text'>
There are two find_freq() functions in clk-rcg.c and clk-rcg2.c
that are almost exactly the same. Consolidate them into one
function to save on some code space.

Cc: Mike Turquette &lt;mturquette@linaro.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Fix PLL rate configurations</title>
<updated>2014-07-15T23:39:00Z</updated>
<author>
<name>Stephen Boyd</name>
</author>
<published>2014-07-15T21:59:21Z</published>
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<id>urn:sha1:5b6b7490af110c2b0df807eddd00ae6290bcf50a</id>
<content type='text'>
Sometimes we need to program PLLs with a fixed rate
configuration during driver probe. Doing this after we register
the PLLs with the clock framework causes the common clock
framework to assume the rate of the PLLs are 0. This causes all
sorts of problems for rate recalculations because the common
clock framework caches the rate once at registration time unless
a flag is set to always recalculate the rates.

Split the qcom_cc_probe() function into two pieces, map and
everything else, so that drivers which need to configure some
PLL rates or otherwise twiddle bits in the clock controller can
do so before registering clocks. This allows us to properly
detect the rates of PLLs that are programmed at boot.

Fixes: 49fc825f0cc2 "clk: qcom: Consolidate common probe code"
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
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