kernel.git/drivers/clk/meson, branch linux-4.15.y

clk: meson: mpll: use 64-bit maths in params_from_rate

2018-04-12T10:31:01Z

[ Upstream commit 86aacdca66774051cbc0958110a48074b57a060b ] "rem * SDM_DEN" can easily overflow on the 32-bit Meson8 and Meson8b SoCs if the "remainder" (after the division operation) is greater than 262143Hz. This is likely to happen since the input clock for the MPLLs on Meson8 and Meson8b is "fixed_pll", which is running at a rate of 2550MHz. One example where this was observed to be problematic was the Ethernet clock calculation (which takes MPLL2 as input). When requesting a rate of 125MHz there is a remainder of 2500000Hz. The resulting MPLL2 rate before this patch was 127488329Hz. The resulting MPLL2 rate after this patch is 124999103Hz. Commit b609338b26f5 ("clk: meson: mpll: use 64bit math in rate_from_params") already fixed a similar issue in rate_from_params. Fixes: 007e6e5c5f01d3 ("clk: meson: mpll: add rw operation") Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman

clk: meson: gxbb: fix wrong clock for SARADC/SANA

2018-03-19T08:09:50Z

[ Upstream commit 75eccf5ed83250c0aeaeeb76f7288254ac0a87b4 ] According to the datasheet, in Meson-GXBB/GXL series, The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. Test passed at gxl-s905x-p212 board. The following published datasheets are wrong and should be updated [1] GXBB v1.1.4 [2] GXL v0.3_20170314 Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Tested-by: Xingyu Chen Signed-off-by: Yixun Lan Signed-off-by: Jerome Brunet Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman

clk: meson: gxbb: Add VPU and VAPB clocks data

2017-10-20T08:34:49Z

The Amlogic Meson GX SoCs needs these two clocks to power up the VPU power domain. These two clocks are similar to the MALI clocks by having a glitch-free mux and two similar clocks with gate, divider and muxes. Acked-by: Jerome Brunet [narmstrong: removed the CLK_IGNORE_UNUSED on muxes and dividers] Signed-off-by: Neil Armstrong

clk: meson: gxbb: Add VPU and VAPB clockids

2017-10-20T08:24:30Z

Add the clkids for the clocks feeding the Video Processing Unit. Acked-by: Jerome Brunet Signed-off-by: Neil Armstrong

Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into clk-next

2017-08-23T22:28:52Z

Pull Amlogic clock driver updates from Neil Armstrong: * meson8b: add the reset controller to the clkc * meson: expose all clk ids * gxbb-aoclk: Add CEC 32k clock * gxbb: add mmc input 0 clocks * meson: fix protection against undefined clks * gxbb: fix audio divider flags * tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson: clk: meson: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb-aoclk: Switch to regmap for register access dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings clk: meson: gxbb: Add sd_emmc clk0 clocks clk: meson: gxbb: fix clk_mclk_i958 divider flags clk: meson: gxbb: fix meson cts_amclk divider flags clk: meson: meson8b: register the built-in reset controller dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb: Add sd_emmc clk0 clkids clk: meson-gxbb: expose almost every clock in the bindings clk: meson8b: expose every clock in the bindings clk: meson: gxbb: fix protection against undefined clks clk: meson: meson8b: fix protection against undefined clks dt-bindings: clock: meson8b: describe the embedded reset controller

clk: meson: gxbb-aoclk: Add CEC 32k clock

2017-08-04T16:02:02Z

The CEC 32K AO Clock is a dual divider with dual counter to provide a more precise 32768Hz clock for the CEC subsystem from the external xtal. Signed-off-by: Neil Armstrong

clk: meson: gxbb-aoclk: Switch to regmap for register access

2017-08-04T16:02:01Z

Switch the aoclk driver to use the new bindings and switch all the registers access to regmap only. Signed-off-by: Neil Armstrong

clk: meson: gxbb: Add sd_emmc clk0 clocks

2017-08-04T16:02:00Z

Input source 0 of the mmc controllers is not directly xtal, as currently described in DT. Each controller is fed by a composite clock (the usual mux, divider and gate). The muxes inputs are the xtal (default) and the fclk_div clocks. These parents, along with the divider, should be able to provide the necessary rates for mmc and nand operation. The input muxes should also be able to take mpll2, mpll3 and gp0_pll but these are precious clocks, needed for other usage. It is better if the mmc does not use these them. For this reason, mpll2, mpll3 and gp0_pll is not listed among the possible parents. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong

clk: meson: gxbb: fix clk_mclk_i958 divider flags

2017-08-04T16:01:59Z

CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 3c277c247eab ("clk: meson: gxbb: add cts_mclk_i958") Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong

clk: meson: gxbb: fix meson cts_amclk divider flags

2017-08-04T16:01:59Z

CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 4087bd4b2170 ("clk: meson: gxbb: add cts_amclk") Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong