kernel.git/drivers/clk/meson/Makefile, branch linux-5.0.y

clk: meson: add clk-input helper function

2018-12-05T10:24:40Z

Add the clock input helper function. Several amlogic clock controllers will now be registering bypass clock input. Instead of copying this code in every of them, let's make an helper function for it Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong [narmstrong: fixed up to apply on Makefile and clkc.h] Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20181204165819.21541-2-jbrunet@baylibre.com

clk: meson: Add vid_pll divider driver

2018-11-23T14:11:56Z

Add support the VID_PLL fully programmable divider used right after the HDMI PLL clock source. It is used to achieve complex fractional division with a programmble bitfield. Signed-off-by: Neil Armstrong Acked-by: Jerome Brunet Link: http://lkml.kernel.org/r/1541516257-16157-2-git-send-email-narmstrong@baylibre.com

clk: meson: remove unused clk-audio-divider driver

2018-07-09T11:48:59Z

clk-audio-divider is no longer used, we can remove it. Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet

clk: meson: axg: add the audio clock controller driver

2018-07-09T11:48:26Z

The axg audio clock controller is the clock generation unit for the amlogic audio subsystem of A113 based SoCs. It may be clocked by 8 different plls provided by the primary clock controller and also by 10 slave bit clocks and 10 slave sample clocks which may be provided by external components, such as audio codecs, through the SoC pads. It contains several muxes, dividers and gates which are fed into the the different devices of the audio subsystem. Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet

clk: meson: add axg audio sclk divider driver

2018-07-09T11:48:25Z

Add a driver to control the clock divider found in the sample clock generator of the axg audio clock controller. The sclk divider accumulates specific features which make the generic divider unsuitable to control it: - zero based divider (div = val + 1), but zero value gates the clock, so minimum divider value is 2. - lrclk variant may adjust the duty cycle depending the divider value and the 'hi' value. Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet

clk: meson: add triple phase clock driver

2018-07-09T11:47:22Z

Add a driver to control the output of the sample clock generator found in the axg audio clock controller. The goal of this driver is to coherently control the phase provided to the different element using the sample clock generator. This simplify the usage of the sample clock generator a lot, without comprising the ability of the SoC. Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet

clk: meson: add clk-phase clock driver

2018-07-09T11:47:22Z

Add a driver based meson clk-regmap to control clock phase on amlogic SoCs Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet

clk: meson-axg: Add AO Clock and Reset controller driver

2018-05-15T12:19:43Z

Adds a Clock and Reset controller driver for the Always-On part of the Amlogic Meson-AXG SoC. Signed-off-by: Qiufang Dai Signed-off-by: Yixun Lan Signed-off-by: Jerome Brunet

clk: meson: aoclk: refactor common code into dedicated file

2018-05-15T12:19:42Z

We try to refactor the common code into one dedicated file, while preparing to add new Meson-AXG aoclk driver, this would help us to better share the code by all aoclk drivers. Suggested-by: Jerome Brunet Signed-off-by: Yixun Lan Signed-off-by: Jerome Brunet

clk: meson: remove obsolete cpu_clk

2018-03-13T09:04:04Z

meson8b cpu_clk has been replaced by a set of divider and mux clocks. meson_cpu_clk is no longer used and can be removed Acked-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong