<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/clk/mediatek/Makefile, branch linux-5.19.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.19.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.19.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2022-04-25T23:59:41Z</updated>
<entry>
<title>clk: mediatek: Add MT8186 ipesys clock support</title>
<updated>2022-04-25T23:59:41Z</updated>
<author>
<name>Chun-Jie Chen</name>
</author>
<published>2022-04-09T13:22:51Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a677bdf8b6aeea56bd545f7d7c1dcf18d0538426'/>
<id>urn:sha1:a677bdf8b6aeea56bd545f7d7c1dcf18d0538426</id>
<content type='text'>
Add MT8186 ipesys clock controller which provides clock gate
control for Image Process Engine.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Miles Chen &lt;miles.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20220409132251.31725-16-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add MT8186 mdpsys clock support</title>
<updated>2022-04-25T23:59:40Z</updated>
<author>
<name>Chun-Jie Chen</name>
</author>
<published>2022-04-09T13:22:50Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8c3adc5d2e14a4c35fcef8afdf777b8d2a99ea60'/>
<id>urn:sha1:8c3adc5d2e14a4c35fcef8afdf777b8d2a99ea60</id>
<content type='text'>
Add MT8186 mdpsys clock controller which provides clock gate
control in Multimedia Data Path.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Miles Chen &lt;miles.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20220409132251.31725-15-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add MT8186 camsys clock support</title>
<updated>2022-04-25T23:59:40Z</updated>
<author>
<name>Chun-Jie Chen</name>
</author>
<published>2022-04-09T13:22:49Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6f2e1208249fde5bfdaac98affff955c49cb5da2'/>
<id>urn:sha1:6f2e1208249fde5bfdaac98affff955c49cb5da2</id>
<content type='text'>
Add MT8186 camsys clock controllers which provide clock gate
control for camera IP blocks.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Miles Chen &lt;miles.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20220409132251.31725-14-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add MT8186 vencsys clock support</title>
<updated>2022-04-25T23:59:40Z</updated>
<author>
<name>Chun-Jie Chen</name>
</author>
<published>2022-04-09T13:22:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=fc2195028363527bd566abd38d84fd63b620c53a'/>
<id>urn:sha1:fc2195028363527bd566abd38d84fd63b620c53a</id>
<content type='text'>
Add MT8186 vencsys clock controller which provide clock gate
control for video encoder.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Miles Chen &lt;miles.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20220409132251.31725-13-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add MT8186 vdecsys clock support</title>
<updated>2022-04-25T23:59:40Z</updated>
<author>
<name>Chun-Jie Chen</name>
</author>
<published>2022-04-09T13:22:47Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7e23620dff94c4956f613f4c032c4140de188349'/>
<id>urn:sha1:7e23620dff94c4956f613f4c032c4140de188349</id>
<content type='text'>
Add MT8186 vdec clock controller which provide clock gate
control for video decoder.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Miles Chen &lt;miles.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20220409132251.31725-12-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add MT8186 imgsys clock support</title>
<updated>2022-04-25T23:59:40Z</updated>
<author>
<name>Chun-Jie Chen</name>
</author>
<published>2022-04-09T13:22:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a6c0c9b8fc91925b2702bac4d04640f894552d37'/>
<id>urn:sha1:a6c0c9b8fc91925b2702bac4d04640f894552d37</id>
<content type='text'>
Add MT8186 imgsys clock controllers which provide clock gate
control for image IP blocks.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Miles Chen &lt;miles.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20220409132251.31725-11-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add MT8186 wpesys clock support</title>
<updated>2022-04-25T23:59:40Z</updated>
<author>
<name>Chun-Jie Chen</name>
</author>
<published>2022-04-09T13:22:45Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b6da76d6eb42757a5e100f309ac8852d407f3c60'/>
<id>urn:sha1:b6da76d6eb42757a5e100f309ac8852d407f3c60</id>
<content type='text'>
Add MT8186 wpesys clock controllers which provide clock gate
control in Wrapping Engine.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Miles Chen &lt;miles.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20220409132251.31725-10-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add MT8186 mmsys clock support</title>
<updated>2022-04-25T23:59:40Z</updated>
<author>
<name>Chun-Jie Chen</name>
</author>
<published>2022-04-09T13:22:44Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c8c36b996f3c1ca0d2e799f67a2cbb5392568a45'/>
<id>urn:sha1:c8c36b996f3c1ca0d2e799f67a2cbb5392568a45</id>
<content type='text'>
Add MT8186 mmsys clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start mmsys clock driver.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Miles Chen &lt;miles.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20220409132251.31725-9-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add MT8186 mfgsys clock support</title>
<updated>2022-04-25T23:59:39Z</updated>
<author>
<name>Chun-Jie Chen</name>
</author>
<published>2022-04-09T13:22:43Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e4a424461c82daab6ef9cbe331862fbcccb292ee'/>
<id>urn:sha1:e4a424461c82daab6ef9cbe331862fbcccb292ee</id>
<content type='text'>
Add MT8186 mfg clock controller which provides clock gate
control for GPU.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Miles Chen &lt;miles.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20220409132251.31725-8-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add MT8186 imp i2c wrapper clock support</title>
<updated>2022-04-25T23:59:39Z</updated>
<author>
<name>Chun-Jie Chen</name>
</author>
<published>2022-04-09T13:22:42Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=66cd0b4b0ce5e1b26e0eb42110e34860fd4a25cf'/>
<id>urn:sha1:66cd0b4b0ce5e1b26e0eb42110e34860fd4a25cf</id>
<content type='text'>
Add MT8186 imp i2c wrapper clock controllers which provide clock gate
control in i2c IP blocks.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Miles Chen &lt;miles.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20220409132251.31725-7-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
</feed>
