kernel.git/drivers/clk/mediatek/Kconfig, branch linux-rolling-stableHosts the 0x221E linux distro kernel.
https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-rolling-stable2025-09-21T16:36:22Zclk: mediatek: Add MT8196 vencsys clock support2025-09-21T16:36:22ZLaura Nao2025-09-15T15:19:47Zurn:sha1:2f66f069999dda4a44c5586805d468b8ac93ac1a
Add support for the MT8196 vencsys clock controller, which provides
clock gate control for the video encoder.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8196 vdecsys clock support2025-09-21T16:36:20ZLaura Nao2025-09-15T15:19:46Zurn:sha1:32ce24a3131b07b4348281f9e34359cb45883b25
Add support for the MT8196 vdecsys clock controller, which provides
clock gate control for the video decoder.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8196 disp0 clock support2025-09-21T16:36:14ZLaura Nao2025-09-15T15:19:41Zurn:sha1:91894f618838339d51c694bd788f16c9b056b1b0
Add support for the MT8196 disp0 clock controller, which provides clock
gate control for the display system. It is integrated with the mtk-mmsys
driver, which registers the disp0 clock driver via
platform_device_register_data().
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8196 mfg clock support2025-09-21T16:36:13ZLaura Nao2025-09-15T15:19:40Zurn:sha1:03dc02f8c7dc6d9d0cebea5f289c7052483353dc
Add support for the MT8196 mfg clock controller, which provides PLL
control for the GPU.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8196 mdpsys clock support2025-09-21T16:36:12ZLaura Nao2025-09-15T15:19:39Zurn:sha1:2a827a7a4c2d45c601d6e2539537c7363c6c8b36
Add support for the MT8196 mdpsys clock controller, which provides clock
gate control for MDP.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> # CLK_OPS_PARENT_ENABLE removal
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8196 mcu clock support2025-09-21T16:36:10ZLaura Nao2025-09-15T15:19:38Zurn:sha1:d4ecae56a8c7d3287a5bcdb2d65f7102ee580ab6
Add support for the MT8196 mcu clock controller, which provides PLL
control for MCU.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8196 I2C clock support2025-09-21T16:36:09ZLaura Nao2025-09-15T15:19:37Zurn:sha1:8f61d9d319915eb84511773dfa57fb0c60ead0f7
Add support for the MT8196 I2C clock controller, which provides clock
gate control for I2C.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8196 pextpsys clock support2025-09-21T16:36:08ZLaura Nao2025-09-15T15:19:36Zurn:sha1:c9b9a66bde91b84157243f8a6fe6ac524868c199
Add support for the MT8196 pextpsys clock controller, which provides
clock gate control for PCIe.
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> # CLK_OPS_PARENT_ENABLE removal
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8196 ufssys clock support2025-09-21T16:36:07ZLaura Nao2025-09-15T15:19:35Zurn:sha1:a74d5e835a9ff3ac56c01e6235e3122b0208ad30
Add support for the MT8196 ufssys clock controller, which provides clock
gate control for UFS.
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8196 apmixedsys clock support2025-09-21T16:36:01ZLaura Nao2025-09-15T15:19:30Zurn:sha1:d78485d63b79dd896301439e57e3dea45db0b575
Add support for the MT8196 apmixedsys clock controller, which provides
PLLs generated from SoC 26m.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>