kernel.git/drivers/clk/ingenic, branch linux-5.11.y

clk: ingenic: Fix divider calculation with div tables

2020-12-20T00:04:58Z

The previous code assumed that a higher hardware value always resulted in a bigger divider, which is correct for the regular clocks, but is an invalid assumption when a divider table is provided for the clock. Perfect example of this is the PLL0_HALF clock, which applies a /2 divider with the hardware value 0, and a /1 divider otherwise. Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables") Cc: # 5.2 Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net Signed-off-by: Stephen Boyd

clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate

2020-10-14T03:04:50Z

Clocks that don't have a divider are in our case all marked with the CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation should modify the value pointed to by parent_rate, in order to propagate the rate change to the parent, as explained in the documentation of clk_set_rate(). Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20200903015048.3091523-5-paul@crapouillou.net Signed-off-by: Stephen Boyd

clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT

2020-10-14T03:04:50Z

The custom clocks have custom functions to round, get or set their rate. Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20200903015048.3091523-4-paul@crapouillou.net Signed-off-by: Stephen Boyd

clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL

2020-10-14T03:04:50Z

CLK_SET_RATE_GATE means that the clock must be gated when being reclocked. This is not the case for the PLLs in Ingenic SoCs. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net Signed-off-by: Stephen Boyd

clk: ingenic: Use readl_poll_timeout instead of custom loop

2020-10-14T03:04:50Z

Use the readl_poll_timeout() function instead of rolling our own busy-wait loops. This makes the code simpler. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20200903015048.3091523-2-paul@crapouillou.net Signed-off-by: Stephen Boyd

clk: ingenic: Use to_clk_info() macro for all clocks

2020-10-14T03:04:50Z

The to_clk_info() previously had a BUG_ON() to check that it was only called for PLL clocks. Yet, all the other clocks were doing the exact same thing the macro does, in-line. Move the to_clk_info() macro to the top of the file, remove the hardcoded BUG_ON(), and use it everywhere it makes sense. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20200903015048.3091523-1-paul@crapouillou.net Signed-off-by: Stephen Boyd

clk: X1000: Add support for calculat REFCLK of USB PHY.

2020-07-28T01:18:14Z

Add functions for calculat the rate of REFCLK, which is needed by USB PHY in Ingenic X1000 SoC. Tested-by: 周正 (Zhou Zheng) Signed-off-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/20200630163852.47267-4-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd

clk: JZ4780: Reformat the code to align it.

2020-07-28T01:18:14Z

Reformat the code (add one level of indentation before the values), to align the code in the macro definition section. Tested-by: 周正 (Zhou Zheng) Signed-off-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/20200630163852.47267-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd

clk: JZ4780: Add functions for enable and disable USB PHY.

2020-07-28T01:18:14Z

Add new functions to "jz4780_otg_phy_ops" to enable or disable the USB PHY in the JZ4780 SoC. Tested-by: 周正 (Zhou Zheng) Signed-off-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/20200630163852.47267-2-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd

clk: Ingenic: Add RTC related clocks for Ingenic SoCs.

2020-07-28T01:17:52Z

The RTC unit in the Ingenic SoCs has two clock sources, one is from an external 32.768kHz clock, and the other is from an external 24MHz/48MHz main clock that is divided by 512. The choice of these two clocks is controlled by the ERCS bit in the OPCR register. The RNG unit will also use this clock. Tested-by: 周正 (Zhou Zheng) Signed-off-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/20200725051136.58220-4-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd