kernel.git/drivers/clk/ingenic, branch linux-5.0.y

clk: ingenic: Fix doc of ingenic_cgu_div_info

2019-03-23T19:11:29Z

commit 7ca4c922aad2e3c46767a12f80d01c6b25337b59 upstream. The 'div' field does not represent a number of bits used to divide (understand: right-shift) the divider, but a number itself used to divide the divider. Signed-off-by: Paul Cercueil Signed-off-by: Maarten ter Huurne Cc: Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: ingenic: Fix round_rate misbehaving with non-integer dividers

2019-03-23T19:11:29Z

commit bc5d922c93491878c44c9216e9d227c7eeb81d7f upstream. Take a parent rate of 180 MHz, and a requested rate of 4.285715 MHz. This results in a theorical divider of 41.999993 which is then rounded up to 42. The .round_rate function would then return (180 MHz / 42) as the clock, rounded down, so 4.285714 MHz. Calling clk_set_rate on 4.285714 MHz would round the rate again, and give a theorical divider of 42,0000028, now rounded up to 43, and the rate returned would be (180 MHz / 43) which is 4.186046 MHz, aka. not what we requested. Fix this by rounding up the divisions. Signed-off-by: Paul Cercueil Tested-by: Maarten ter Huurne Cc: Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: Add Ingenic jz4725b CGU driver

2018-10-16T22:19:48Z

Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd

clk: ingenic: Add proper Kconfig entries

2018-10-16T22:19:15Z

Previously, the CGU code corresponding to the SoC for which we're compiling the kernel was the only one enabled, which made it impossible to build one kernel that supports them all. Now, it is possible to select more than one SoC to support. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd

clk: ingenic: Add missing flag for UDC clock

2018-07-06T18:47:28Z

The UDC clock of the JZ4740 SoC can be gated, but the data structure representing it was missing the CGU_CLK_GATE flag to make it work. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd

clk: ingenic: Fix incorrect data for the i2s clock

2018-07-06T18:47:27Z

The register field for configuring the divider for the i2s clock occupies the bits [8-0], which means 9 bits and not 8. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd

docs: Fix some broken references

2018-06-15T21:10:01Z

As we move stuff around, some doc references are broken. Fix some of them via this script: ./scripts/documentation-file-ref-check --fix Manually checked if the produced result is valid, removing a few false-positives. Acked-by: Takashi Iwai Acked-by: Masami Hiramatsu Acked-by: Stephen Boyd Acked-by: Charles Keepax Acked-by: Mathieu Poirier Reviewed-by: Coly Li Signed-off-by: Mauro Carvalho Chehab Acked-by: Jonathan Corbet

clk: ingenic: jz4770: Add 150us delay after enabling VPU clock

2018-06-02T06:21:39Z

This is required, as we must not use the AHB1 bus before it is stable. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd

clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock

2018-06-02T06:21:33Z

This was broken before, because the AHB1 bus was enabled before the VPU clock was ungated, while it must be done afterwards. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd

clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle

2018-06-02T06:21:33Z

When the main processor goes idle, by default its clock is stopped. However, this also stops the clock of the co-processor. Here, if the C1CLK clock is enabled, we disable this functionality. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd