<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/ata/ahci.c, branch linux-5.8.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.8.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.8.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2020-04-16T16:26:52Z</updated>
<entry>
<title>ahci: Add Intel Comet Lake PCH-U PCI ID</title>
<updated>2020-04-16T16:26:52Z</updated>
<author>
<name>Kai-Heng Feng</name>
</author>
<published>2020-04-16T06:35:40Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1f2ef049cb11c68134ce699f749f16ca8d34468e'/>
<id>urn:sha1:1f2ef049cb11c68134ce699f749f16ca8d34468e</id>
<content type='text'>
Add Intel Comet Lake PCH-U PCI ID to the list of supported controllers.

Set default SATA LPM so the SoC can enter S0ix.

Signed-off-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Signed-off-by: Jens Axboe &lt;axboe@kernel.dk&gt;
</content>
</entry>
<entry>
<title>ahci: Add Intel Comet Lake PCH RAID PCI ID</title>
<updated>2020-04-09T15:31:38Z</updated>
<author>
<name>Jian-Hong Pan</name>
</author>
<published>2019-11-28T08:10:42Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7667e63c8af90e287f9e2d070599024cbabe63f5'/>
<id>urn:sha1:7667e63c8af90e287f9e2d070599024cbabe63f5</id>
<content type='text'>
Intel Comet Lake should use the default LPM policy for mobile chipsets.
So, add the PCI ID to the driver list of supported devices.

Signed-off-by: Jian-Hong Pan &lt;jian-hong@endlessm.com&gt;
Signed-off-by: Jens Axboe &lt;axboe@kernel.dk&gt;
</content>
</entry>
<entry>
<title>ata: ahci: Add sysfs attribute to show remapped NVMe device count</title>
<updated>2020-04-07T22:07:38Z</updated>
<author>
<name>Kai-Heng Feng</name>
</author>
<published>2020-02-07T10:00:16Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=894fba7f434a408ec3f4d4164d2b300ee9263d38'/>
<id>urn:sha1:894fba7f434a408ec3f4d4164d2b300ee9263d38</id>
<content type='text'>
Add a new sysfs attribute to show how many NVMe devices are remapped.

Userspace like distro installer can use this info to ask user to change
the BIOS setting.

Signed-off-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Signed-off-by: Jens Axboe &lt;axboe@kernel.dk&gt;
</content>
</entry>
<entry>
<title>ahci: Add Intel Comet Lake PCH-V PCI ID</title>
<updated>2020-03-25T16:29:35Z</updated>
<author>
<name>Mika Westerberg</name>
</author>
<published>2020-02-28T10:50:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=58c42b0b0d6eabb1db52f0f9e4b6017e81132055'/>
<id>urn:sha1:58c42b0b0d6eabb1db52f0f9e4b6017e81132055</id>
<content type='text'>
Add Intel Comet Lake PCH-V PCI ID to the list of supported controllers.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Jens Axboe &lt;axboe@kernel.dk&gt;
</content>
</entry>
<entry>
<title>ahci: Add Intel Comet Lake PCH-H PCI ID</title>
<updated>2020-03-25T16:29:35Z</updated>
<author>
<name>Mika Westerberg</name>
</author>
<published>2020-02-27T14:32:59Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5e125d13371b3049d238a4bf5f2108bfbfe8a900'/>
<id>urn:sha1:5e125d13371b3049d238a4bf5f2108bfbfe8a900</id>
<content type='text'>
Add Intel Comet Lake PCH-H PCI ID to the list of supported controllers.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Jens Axboe &lt;axboe@kernel.dk&gt;
</content>
</entry>
<entry>
<title>ahci: Add Intel Comet Lake H RAID PCI ID</title>
<updated>2020-03-25T16:29:35Z</updated>
<author>
<name>Kai-Heng Feng</name>
</author>
<published>2020-02-27T12:28:22Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=32d2545462c6cede998267b86e57cda5d1dc2225'/>
<id>urn:sha1:32d2545462c6cede998267b86e57cda5d1dc2225</id>
<content type='text'>
Add the PCI ID to the driver list to support this new device.

Cc: stable@vger.kernel.org
Signed-off-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Signed-off-by: Jens Axboe &lt;axboe@kernel.dk&gt;
</content>
</entry>
<entry>
<title>AHCI: Add support for Loongson 7A1000 SATA controller</title>
<updated>2020-03-12T13:44:19Z</updated>
<author>
<name>Tiezhu Yang</name>
</author>
<published>2020-03-10T12:50:08Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e49bd683e00bcc636bf2df79d4c8a0bda0314dc0'/>
<id>urn:sha1:e49bd683e00bcc636bf2df79d4c8a0bda0314dc0</id>
<content type='text'>
Loongson 7A1000 SATA controller uses BAR0 as the base address register.

Signed-off-by: Tiezhu Yang &lt;yangtiezhu@loongson.cn&gt;
Signed-off-by: Jens Axboe &lt;axboe@kernel.dk&gt;
</content>
</entry>
<entry>
<title>ata: ahci: Add shutdown to freeze hardware resources of ahci</title>
<updated>2020-01-30T04:02:15Z</updated>
<author>
<name>Prabhakar Kushwaha</name>
</author>
<published>2020-01-25T03:37:29Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=10a663a1b15134a5a714aa515e11425a44d4fdf7'/>
<id>urn:sha1:10a663a1b15134a5a714aa515e11425a44d4fdf7</id>
<content type='text'>
device_shutdown() called from reboot or power_shutdown expect
all devices to be shutdown. Same is true for even ahci pci driver.
As no ahci shutdown function is implemented, the ata subsystem
always remains alive with DMA &amp; interrupt support. File system
related calls should not be honored after device_shutdown().

So defining ahci pci driver shutdown to freeze hardware (mask
interrupt, stop DMA engine and free DMA resources).

Signed-off-by: Prabhakar Kushwaha &lt;pkushwaha@marvell.com&gt;
Signed-off-by: Jens Axboe &lt;axboe@kernel.dk&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux; tag 'dma-mapping-5.5' of git://git.infradead.org/users/hch/dma-mapping</title>
<updated>2019-11-28T19:16:43Z</updated>
<author>
<name>Linus Torvalds</name>
</author>
<published>2019-11-28T19:16:43Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=81b6b96475ac7a4ebfceae9f16fb3758327adbfe'/>
<id>urn:sha1:81b6b96475ac7a4ebfceae9f16fb3758327adbfe</id>
<content type='text'>
Pull dma-mapping updates from Christoph Hellwig:

 - improve dma-debug scalability (Eric Dumazet)

 - tiny dma-debug cleanup (Dan Carpenter)

 - check for vmap memory in dma_map_single (Kees Cook)

 - check for dma_addr_t overflows in dma-direct when using DMA offsets
   (Nicolas Saenz Julienne)

 - switch the x86 sta2x11 SOC to use more generic DMA code (Nicolas
   Saenz Julienne)

 - fix arm-nommu dma-ranges handling (Vladimir Murzin)

 - use __initdata in CMA (Shyam Saini)

 - replace the bus dma mask with a limit (Nicolas Saenz Julienne)

 - merge the remapping helpers into the main dma-direct flow (me)

 - switch xtensa to the generic dma remap handling (me)

 - various cleanups around dma_capable (me)

 - remove unused dev arguments to various dma-noncoherent helpers (me)

* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux:

* tag 'dma-mapping-5.5' of git://git.infradead.org/users/hch/dma-mapping: (22 commits)
  dma-mapping: treat dev-&gt;bus_dma_mask as a DMA limit
  dma-direct: exclude dma_direct_map_resource from the min_low_pfn check
  dma-direct: don't check swiotlb=force in dma_direct_map_resource
  dma-debug: clean up put_hash_bucket()
  powerpc: remove support for NULL dev in __phys_to_dma / __dma_to_phys
  dma-direct: avoid a forward declaration for phys_to_dma
  dma-direct: unify the dma_capable definitions
  dma-mapping: drop the dev argument to arch_sync_dma_for_*
  x86/PCI: sta2x11: use default DMA address translation
  dma-direct: check for overflows on 32 bit DMA addresses
  dma-debug: increase HASH_SIZE
  dma-debug: reorder struct dma_debug_entry fields
  xtensa: use the generic uncached segment support
  dma-mapping: merge the generic remapping helpers into dma-direct
  dma-direct: provide mmap and get_sgtable method overrides
  dma-direct: remove the dma_handle argument to __dma_direct_alloc_pages
  dma-direct: remove __dma_direct_free_pages
  usb: core: Remove redundant vmap checks
  kernel: dma-contiguous: mark CMA parameters __initdata/__initconst
  dma-debug: add a schedule point in debug_dma_dump_mappings()
  ...
</content>
</entry>
<entry>
<title>dma-mapping: treat dev-&gt;bus_dma_mask as a DMA limit</title>
<updated>2019-11-21T17:14:35Z</updated>
<author>
<name>Nicolas Saenz Julienne</name>
</author>
<published>2019-11-21T09:26:44Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a7ba70f1787f977f970cd116076c6fce4b9e01cc'/>
<id>urn:sha1:a7ba70f1787f977f970cd116076c6fce4b9e01cc</id>
<content type='text'>
Using a mask to represent bus DMA constraints has a set of limitations.
The biggest one being it can only hold a power of two (minus one). The
DMA mapping code is already aware of this and treats dev-&gt;bus_dma_mask
as a limit. This quirk is already used by some architectures although
still rare.

With the introduction of the Raspberry Pi 4 we've found a new contender
for the use of bus DMA limits, as its PCIe bus can only address the
lower 3GB of memory (of a total of 4GB). This is impossible to represent
with a mask. To make things worse the device-tree code rounds non power
of two bus DMA limits to the next power of two, which is unacceptable in
this case.

In the light of this, rename dev-&gt;bus_dma_mask to dev-&gt;bus_dma_limit all
over the tree and treat it as such. Note that dev-&gt;bus_dma_limit should
contain the higher accessible DMA address.

Signed-off-by: Nicolas Saenz Julienne &lt;nsaenzjulienne@suse.de&gt;
Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
</content>
</entry>
</feed>
