<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/acpi/riscv, branch linux-6.10.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.10.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.10.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2024-03-20T01:30:54Z</updated>
<entry>
<title>ACPI: RISC-V: Add CPPC driver</title>
<updated>2024-03-20T01:30:54Z</updated>
<author>
<name>Sunil V L</name>
</author>
<published>2024-02-08T03:44:12Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=30f3ffbee86b576705aabdd9093165a49cd66011'/>
<id>urn:sha1:30f3ffbee86b576705aabdd9093165a49cd66011</id>
<content type='text'>
Add cpufreq driver based on ACPI CPPC for RISC-V. The driver uses either
SBI CPPC interfaces or the CSRs to access the CPPC registers as defined
by the RISC-V FFH spec.

Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Reviewed-by: Pierre Gondois &lt;pierre.gondois@arm.com&gt;
Acked-by: Rafael J. Wysocki &lt;rafael@kernel.org&gt;
Acked-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
Link: https://lore.kernel.org/r/20240208034414.22579-2-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>ACPI: RISC-V: Add LPI driver</title>
<updated>2024-03-20T00:51:39Z</updated>
<author>
<name>Sunil V L</name>
</author>
<published>2024-01-18T06:29:29Z</published>
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<id>urn:sha1:4877fc92142f635be418d8c915eb48ef87681108</id>
<content type='text'>
Enable Low Power Idle (LPI) based cpuidle driver for RISC-V platforms.
It depends on SBI HSM calls for idle state transitions.

Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Link: https://lore.kernel.org/r/20240118062930.245937-3-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: ACPI: RHCT: Add function to get CBO block sizes</title>
<updated>2023-10-26T16:40:33Z</updated>
<author>
<name>Sunil V L</name>
</author>
<published>2023-10-18T12:40:06Z</published>
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<id>urn:sha1:9ca87564190cf0e5bb72695fb0db9947fcc47843</id>
<content type='text'>
Cache Block Operation (CBO) related block size in ACPI is provided by RHCT.
Add support to read the CMO node in RHCT to get this information.

Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20231018124007.1306159-4-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: ACPI: Update the return value of acpi_get_rhct()</title>
<updated>2023-10-26T16:40:32Z</updated>
<author>
<name>Sunil V L</name>
</author>
<published>2023-10-18T12:40:05Z</published>
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<id>urn:sha1:a06835227280436c1aae021a3f43d3abfcba3835</id>
<content type='text'>
acpi_get_rhct() currently returns pointer to acpi_table_header
structure. But since this is specific to RHCT, return pointer to
acpi_table_rhct structure itself.

Suggested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20231018124007.1306159-3-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>drivers/acpi: RISC-V: Add RHCT related code</title>
<updated>2023-06-01T15:45:04Z</updated>
<author>
<name>Sunil V L</name>
</author>
<published>2023-05-15T05:49:17Z</published>
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<id>urn:sha1:e6b9d8eddb1772d99a676a906d42865293934edd</id>
<content type='text'>
RHCT is a new table defined for RISC-V to communicate the
features of the CPU to the OS. Create a new architecture folder
in drivers/acpi and add RHCT parsing code.

Signed-off-by: Sunil V L &lt;sunilvl@ventanamicro.com&gt;
Acked-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20230515054928.2079268-11-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
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