kernel.git/arch/xtensa/mm/cache.c, branch linux-4.4.y

xtensa: disable preemption around cache alias management calls

2020-11-24T11:48:12Z

commit 3a860d165eb5f4d7cf0bf81ef6a5b5c5e1754422 upstream. Although cache alias management calls set up and tear down TLB entries and fast_second_level_miss is able to restore TLB entry should it be evicted they absolutely cannot preempt each other because they use the same TLBTEMP area for different purposes. Disable preemption around all cache alias management calls to enforce that. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov Signed-off-by: Greg Kroah-Hartman

xtensa: fix preemption in {clear,copy}_user_highpage

2016-04-12T16:08:55Z

commit a67cc9aa2dfc6e66addf240bbd79e16e01565e81 upstream. Disabling pagefault makes little sense there, preemption disabling is what was meant. Signed-off-by: Max Filippov Signed-off-by: Greg Kroah-Hartman

xtensa: support highmem in aliasing cache flushing code

2014-08-14T07:59:23Z

Use __flush_invalidate_dcache_page_alias with alias set to color of the page physical address instead of __flush_invalidate_dcache_page: this works for high memory pages and mapping/unmapping to the TLBTEMP area is virtually free. Allow building configurations with aliasing cache and highmem enabled. Signed-off-by: Max Filippov

xtensa: implement clear_user_highpage and copy_user_highpage

2014-08-14T07:59:20Z

Existing clear_user_page and copy_user_page cannot be used with highmem because they calculate physical page address from its virtual address and do it incorrectly in case of high memory page mapped with kmap_atomic. Also kmap is not needed, as most likely userspace mapping color would be different from the kmapped color. Provide clear_user_highpage and copy_user_highpage functions that determine if temporary mapping is needed for the pages. Move most of the logic of the former clear_user_page and copy_user_page to xtensa/mm/cache.c only leaving temporary mapping setup, invalidation and clearing/copying in the xtensa/mm/misc.S. Rename these functions to clear_page_alias and copy_page_alias. Signed-off-by: Max Filippov

xtensa: add HIGHMEM support

2014-04-06T17:29:21Z

Introduce fixmap area just below the vmalloc region. Use it for atomic mapping of high memory pages. High memory on cores with cache aliasing is not supported and is still to be implemented. Fail build for such configurations for now. Signed-off-by: Max Filippov

xtensa: add SMP support

2014-01-14T18:19:58Z

This is largely based on SMP code from the xtensa-2.6.29-smp tree by Piet Delaney, Marc Gauthier, Joe Taylor, Christian Zankel (and possibly other Tensilica folks). Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: clean up files to make them code-style compliant

2012-12-19T05:10:25Z

Remove heading and trailing spaces, trim trailing lines, and wrap lines that are longer than 80 characters. Signed-off-by: Chris Zankel

MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself

2010-02-20T16:41:46Z

On VIVT ARM, when we have multiple shared mappings of the same file in the same MM, we need to ensure that we have coherency across all copies. We do this via make_coherent() by making the pages uncacheable. This used to work fine, until we allowed highmem with highpte - we now have a page table which is mapped as required, and is not available for modification via update_mmu_cache(). Ralf Beache suggested getting rid of the PTE value passed to update_mmu_cache(): On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables to construct a pointer to the pte again. Passing a pte_t * is much more elegant. Maybe we might even replace the pte argument with the pte_t? Ben Herrenschmidt would also like the pte pointer for PowerPC: Passing the ptep in there is exactly what I want. I want that -instead- of the PTE value, because I have issue on some ppc cases, for I$/D$ coherency, where set_pte_at() may decide to mask out the _PAGE_EXEC. So, pass in the mapped page table pointer into update_mmu_cache(), and remove the PTE value, updating all implementations and call sites to suit. Includes a fix from Stephen Rothwell: sparc: fix fallout from update_mmu_cache API change Signed-off-by: Stephen Rothwell Acked-by: Benjamin Herrenschmidt Signed-off-by: Russell King

[XTENSA] Flush the page-address in update-mmu instead of user-address

2008-02-14T00:58:51Z

The TLB entry for the user address doesn't exist at the time we want to flush the caches, so use the page address. Note that processor configurations with cache-aliasing issues are treated separately. Signed-off-by: Chris Zankel

[XTENSA] Remove duplicate includes.

2008-02-13T23:05:35Z

Signed-off-by: Lucas Woods Signed-off-by: Andrew Morton Signed-off-by: Christian Zankel