kernel.git/arch/xtensa/mm/cache.c, branch linux-2.6.25.y

[XTENSA] Flush the page-address in update-mmu instead of user-address

2008-02-14T00:58:51Z

The TLB entry for the user address doesn't exist at the time we want to flush the caches, so use the page address. Note that processor configurations with cache-aliasing issues are treated separately. Signed-off-by: Chris Zankel

[XTENSA] Remove duplicate includes.

2008-02-13T23:05:35Z

Signed-off-by: Lucas Woods Signed-off-by: Andrew Morton Signed-off-by: Christian Zankel

[XTENSA] Add support for cache-aliasing

2007-08-27T20:54:16Z

Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel