<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/x86/kernel/fpu/regset.c, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-rolling-stable</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-rolling-stable'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2025-04-14T06:18:29Z</updated>
<entry>
<title>x86/fpu: Convert task_struct::thread.fpu accesses to use x86_task_fpu()</title>
<updated>2025-04-14T06:18:29Z</updated>
<author>
<name>Ingo Molnar</name>
</author>
<published>2025-04-09T21:11:21Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e3bfa3859936da3edd1e16d0b74fdaaa19bb5087'/>
<id>urn:sha1:e3bfa3859936da3edd1e16d0b74fdaaa19bb5087</id>
<content type='text'>
This will make the removal of the task_struct::thread.fpu array
easier.

No change in functionality - code generated before and after this
commit is identical on x86-defconfig:

  kepler:~/tip&gt; diff -up vmlinux.before.asm vmlinux.after.asm
  kepler:~/tip&gt;

Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Cc: Andy Lutomirski &lt;luto@kernel.org&gt;
Cc: Brian Gerst &lt;brgerst@gmail.com&gt;
Cc: Chang S. Bae &lt;chang.seok.bae@intel.com&gt;
Cc: H. Peter Anvin &lt;hpa@zytor.com&gt;
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Cc: Oleg Nesterov &lt;oleg@redhat.com&gt;
Link: https://lore.kernel.org/r/20250409211127.3544993-3-mingo@kernel.org
</content>
</entry>
<entry>
<title>x86/fpu: Ensure shadow stack is active before "getting" registers</title>
<updated>2025-01-07T23:55:51Z</updated>
<author>
<name>Rick Edgecombe</name>
</author>
<published>2025-01-07T23:30:56Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a9d9c33132d49329ada647e4514d210d15e31d81'/>
<id>urn:sha1:a9d9c33132d49329ada647e4514d210d15e31d81</id>
<content type='text'>
The x86 shadow stack support has its own set of registers. Those registers
are XSAVE-managed, but they are "supervisor state components" which means
that userspace can not touch them with XSAVE/XRSTOR.  It also means that
they are not accessible from the existing ptrace ABI for XSAVE state.
Thus, there is a new ptrace get/set interface for it.

The regset code that ptrace uses provides an -&gt;active() handler in
addition to the get/set ones. For shadow stack this -&gt;active() handler
verifies that shadow stack is enabled via the ARCH_SHSTK_SHSTK bit in the
thread struct. The -&gt;active() handler is checked from some call sites of
the regset get/set handlers, but not the ptrace ones. This was not
understood when shadow stack support was put in place.

As a result, both the set/get handlers can be called with
XFEATURE_CET_USER in its init state, which would cause get_xsave_addr() to
return NULL and trigger a WARN_ON(). The ssp_set() handler luckily has an
ssp_active() check to avoid surprising the kernel with shadow stack
behavior when the kernel is not ready for it (ARCH_SHSTK_SHSTK==0). That
check just happened to avoid the warning.

But the -&gt;get() side wasn't so lucky. It can be called with shadow stacks
disabled, triggering the warning in practice, as reported by Christina
Schimpe:

WARNING: CPU: 5 PID: 1773 at arch/x86/kernel/fpu/regset.c:198 ssp_get+0x89/0xa0
[...]
Call Trace:
&lt;TASK&gt;
? show_regs+0x6e/0x80
? ssp_get+0x89/0xa0
? __warn+0x91/0x150
? ssp_get+0x89/0xa0
? report_bug+0x19d/0x1b0
? handle_bug+0x46/0x80
? exc_invalid_op+0x1d/0x80
? asm_exc_invalid_op+0x1f/0x30
? __pfx_ssp_get+0x10/0x10
? ssp_get+0x89/0xa0
? ssp_get+0x52/0xa0
__regset_get+0xad/0xf0
copy_regset_to_user+0x52/0xc0
ptrace_regset+0x119/0x140
ptrace_request+0x13c/0x850
? wait_task_inactive+0x142/0x1d0
? do_syscall_64+0x6d/0x90
arch_ptrace+0x102/0x300
[...]

Ensure that shadow stacks are active in a thread before looking them up
in the XSAVE buffer. Since ARCH_SHSTK_SHSTK and user_ssp[SHSTK_EN] are
set at the same time, the active check ensures that there will be
something to find in the XSAVE buffer.

[ dhansen: changelog/subject tweaks ]

Fixes: 2fab02b25ae7 ("x86: Add PTRACE interface for shadow stack")
Reported-by: Christina Schimpe &lt;christina.schimpe@intel.com&gt;
Signed-off-by: Rick Edgecombe &lt;rick.p.edgecombe@intel.com&gt;
Signed-off-by: Dave Hansen &lt;dave.hansen@linux.intel.com&gt;
Tested-by: Christina Schimpe &lt;christina.schimpe@intel.com&gt;
Cc:stable@vger.kernel.org
Link: https://lore.kernel.org/all/20250107233056.235536-1-rick.p.edgecombe%40intel.com
</content>
</entry>
<entry>
<title>x86: Add PTRACE interface for shadow stack</title>
<updated>2023-08-02T22:01:51Z</updated>
<author>
<name>Rick Edgecombe</name>
</author>
<published>2023-06-13T00:11:06Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2fab02b25ae7cf5f714ab456b03d9a3fe5ae98c9'/>
<id>urn:sha1:2fab02b25ae7cf5f714ab456b03d9a3fe5ae98c9</id>
<content type='text'>
Some applications (like GDB) would like to tweak shadow stack state via
ptrace. This allows for existing functionality to continue to work for
seized shadow stack applications. Provide a regset interface for
manipulating the shadow stack pointer (SSP).

There is already ptrace functionality for accessing xstate, but this
does not include supervisor xfeatures. So there is not a completely
clear place for where to put the shadow stack state. Adding it to the
user xfeatures regset would complicate that code, as it currently shares
logic with signals which should not have supervisor features.

Don't add a general supervisor xfeature regset like the user one,
because it is better to maintain flexibility for other supervisor
xfeatures to define their own interface. For example, an xfeature may
decide not to expose all of it's state to userspace, as is actually the
case for  shadow stack ptrace functionality. A lot of enum values remain
to be used, so just put it in dedicated shadow stack regset.

The only downside to not having a generic supervisor xfeature regset,
is that apps need to be enlightened of any new supervisor xfeature
exposed this way (i.e. they can't try to have generic save/restore
logic). But maybe that is a good thing, because they have to think
through each new xfeature instead of encountering issues when a new
supervisor xfeature was added.

By adding a shadow stack regset, it also has the effect of including the
shadow stack state in a core dump, which could be useful for debugging.

The shadow stack specific xstate includes the SSP, and the shadow stack
and WRSS enablement status. Enabling shadow stack or WRSS in the kernel
involves more than just flipping the bit. The kernel is made aware that
it has to do extra things when cloning or handling signals. That logic
is triggered off of separate feature enablement state kept in the task
struct. So the flipping on HW shadow stack enforcement without notifying
the kernel to change its behavior would severely limit what an application
could do without crashing, and the results would depend on kernel
internal implementation details. There is also no known use for controlling
this state via ptrace today. So only expose the SSP, which is something
that userspace already has indirect control over.

Co-developed-by: Yu-cheng Yu &lt;yu-cheng.yu@intel.com&gt;
Signed-off-by: Yu-cheng Yu &lt;yu-cheng.yu@intel.com&gt;
Signed-off-by: Rick Edgecombe &lt;rick.p.edgecombe@intel.com&gt;
Signed-off-by: Dave Hansen &lt;dave.hansen@linux.intel.com&gt;
Reviewed-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Reviewed-by: Kees Cook &lt;keescook@chromium.org&gt;
Acked-by: Mike Rapoport (IBM) &lt;rppt@kernel.org&gt;
Tested-by: Pengfei Xu &lt;pengfei.xu@intel.com&gt;
Tested-by: John Allen &lt;john.allen@amd.com&gt;
Tested-by: Kees Cook &lt;keescook@chromium.org&gt;
Link: https://lore.kernel.org/all/20230613001108.3040476-41-rick.p.edgecombe%40intel.com
</content>
</entry>
<entry>
<title>x86/fpu: Add a pkru argument to copy_uabi_from_kernel_to_xstate().</title>
<updated>2022-11-16T23:03:01Z</updated>
<author>
<name>Kyle Huey</name>
</author>
<published>2022-11-15T23:09:28Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1c813ce0305571e1b2e4cc4acca451da9e6ad18f'/>
<id>urn:sha1:1c813ce0305571e1b2e4cc4acca451da9e6ad18f</id>
<content type='text'>
Both KVM (through KVM_SET_XSTATE) and ptrace (through PTRACE_SETREGSET
with NT_X86_XSTATE) ultimately call copy_uabi_from_kernel_to_xstate(),
but the canonical locations for the current PKRU value for KVM guests
and processes in a ptrace stop are different (in the kvm_vcpu_arch and
the thread_state structs respectively).

In preparation for eventually handling PKRU in
copy_uabi_to_xstate, pass in a pointer to the PKRU location.

Signed-off-by: Kyle Huey &lt;me@kylehuey.com&gt;
Signed-off-by: Dave Hansen &lt;dave.hansen@linux.intel.com&gt;
Link: https://lore.kernel.org/all/20221115230932.7126-3-khuey%40kylehuey.com
</content>
</entry>
<entry>
<title>x86/ptrace: Fix xfpregs_set()'s incorrect xmm clearing</title>
<updated>2022-02-18T10:23:21Z</updated>
<author>
<name>Andy Lutomirski</name>
</author>
<published>2022-02-14T12:05:49Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=44cad52cc14ae10062f142ec16ede489bccf4469'/>
<id>urn:sha1:44cad52cc14ae10062f142ec16ede489bccf4469</id>
<content type='text'>
xfpregs_set() handles 32-bit REGSET_XFP and 64-bit REGSET_FP. The actual
code treats these regsets as modern FX state (i.e. the beginning part of
XSTATE). The declarations of the regsets thought they were the legacy
i387 format. The code thought they were the 32-bit (no xmm8..15) variant
of XSTATE and, for good measure, made the high bits disappear by zeroing
the wrong part of the buffer. The latter broke ptrace, and everything
else confused anyone trying to understand the code. In particular, the
nonsense definitions of the regsets confused me when I wrote this code.

Clean this all up. Change the declarations to match reality (which
shouldn't change the generated code, let alone the ABI) and fix
xfpregs_set() to clear the correct bits and to only do so for 32-bit
callers.

Fixes: 6164331d15f7 ("x86/fpu: Rewrite xfpregs_set()")
Reported-by: Luís Ferreira &lt;contact@lsferreira.net&gt;
Signed-off-by: Andy Lutomirski &lt;luto@kernel.org&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Cc: &lt;stable@vger.kernel.org&gt;
Link: https://bugzilla.kernel.org/show_bug.cgi?id=215524
Link: https://lore.kernel.org/r/YgpFnZpF01WwR8wU@zn.tnic
</content>
</entry>
<entry>
<title>x86/fpu: Move xstate size to fpu_*_cfg</title>
<updated>2021-10-21T17:38:55Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2021-10-14T23:09:34Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2bd264bce238cedbf00bde1f28ad51ba45b9114e'/>
<id>urn:sha1:2bd264bce238cedbf00bde1f28ad51ba45b9114e</id>
<content type='text'>
Use the new kernel and user space config storage to store and retrieve the
XSTATE buffer sizes. The default and the maximum size are the same for now,
but will change when support for dynamically enabled features is added.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Link: https://lkml.kernel.org/r/20211014230739.296830097@linutronix.de
</content>
</entry>
<entry>
<title>x86/fpu/xstate: Use fpstate for copy_uabi_to_xstate()</title>
<updated>2021-10-21T12:24:14Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2021-10-13T14:55:55Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=49e4eb4125d506937e52e10c34c8cafd93ab0ed6'/>
<id>urn:sha1:49e4eb4125d506937e52e10c34c8cafd93ab0ed6</id>
<content type='text'>
Prepare for dynamically enabled states per task. The function needs to
retrieve the features and sizes which are valid in a fpstate
context. Retrieve them from fpstate.

Move the function declarations to the core header as they are not
required anywhere else.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Link: https://lkml.kernel.org/r/20211013145323.233529986@linutronix.de
</content>
</entry>
<entry>
<title>x86/fpu/regset: Convert to fpstate</title>
<updated>2021-10-20T20:35:29Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2021-10-13T14:55:36Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=caee31a36c33ed7788d0b3d93a663860157f6c55'/>
<id>urn:sha1:caee31a36c33ed7788d0b3d93a663860157f6c55</id>
<content type='text'>
Convert regset related code to the new register storage mechanism in
preparation for dynamically sized buffers.

No functional change.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Link: https://lkml.kernel.org/r/20211013145322.555239736@linutronix.de
</content>
</entry>
<entry>
<title>x86/fpu: Replace the includes of fpu/internal.h</title>
<updated>2021-10-20T13:27:29Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2021-10-15T01:16:39Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b56d2795b29792c465cc8ef036abad5127a003fb'/>
<id>urn:sha1:b56d2795b29792c465cc8ef036abad5127a003fb</id>
<content type='text'>
Now that the file is empty, fixup all references with the proper includes
and delete the former kitchen sink.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Link: https://lkml.kernel.org/r/20211015011540.001197214@linutronix.de
</content>
</entry>
<entry>
<title>x86/fpu: Move mxcsr related code to core</title>
<updated>2021-10-20T13:27:28Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2021-10-15T01:16:31Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d9d005f32aac7362a1998f4b7fdf8874e91546bd'/>
<id>urn:sha1:d9d005f32aac7362a1998f4b7fdf8874e91546bd</id>
<content type='text'>
No need to expose that to code which only needs the XCR0 accessors.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Link: https://lkml.kernel.org/r/20211015011539.740012411@linutronix.de
</content>
</entry>
</feed>
