<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/x86/kernel/cpu, branch linux-4.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.16.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.16.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2018-06-25T23:54:05Z</updated>
<entry>
<title>x86/intel_rdt: Enable CMT and MBM on new Skylake stepping</title>
<updated>2018-06-25T23:54:05Z</updated>
<author>
<name>Tony Luck</name>
</author>
<published>2018-06-08T16:07:32Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=4ea9a1cd0fc96f046f1131fa85932f1b6ef7923d'/>
<id>urn:sha1:4ea9a1cd0fc96f046f1131fa85932f1b6ef7923d</id>
<content type='text'>
commit 1d9f3e20a56d33e55748552aeec597f58542f92d upstream.

New stepping of Skylake has fixes for cache occupancy and memory
bandwidth monitoring.

Update the code to enable these by default on newer steppings.

Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Cc: stable@vger.kernel.org # v4.14
Cc: Vikas Shivappa &lt;vikas.shivappa@linux.intel.com&gt;
Link: https://lkml.kernel.org/r/20180608160732.9842-1-tony.luck@intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>x86/MCE: Fix stack out-of-bounds write in mce-inject.c: Flags_read()</title>
<updated>2018-06-25T23:53:59Z</updated>
<author>
<name>Tony Luck</name>
</author>
<published>2018-04-27T16:37:08Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cfa51df5a79074e27d2abf2dca6daf7faef14d45'/>
<id>urn:sha1:cfa51df5a79074e27d2abf2dca6daf7faef14d45</id>
<content type='text'>
commit 985c78d3ff8e9c74450fa2bb08eb55e680d999ca upstream.

Each of the strings that we want to put into the buf[MAX_FLAG_OPT_SIZE]
in flags_read() is two characters long. But the sprintf() adds
a trailing newline and will add a terminating NUL byte. So
MAX_FLAG_OPT_SIZE needs to be 4.

sprintf() calls vsnprintf() and *that* does return:

" * The return value is the number of characters which would
 * be generated for the given input, excluding the trailing
 * '\0', as per ISO C99."

Note the "excluding".

Reported-by: Dmitry Vyukov &lt;dvyukov@google.com&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: stable@vger.kernel.org
Cc: linux-edac &lt;linux-edac@vger.kernel.org&gt;
Link: http://lkml.kernel.org/r/20180427163707.ktaiysvbk3yhk4wm@agluck-desk
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>x86/cpu/intel: Add missing TLB cpuid values</title>
<updated>2018-06-20T19:01:27Z</updated>
<author>
<name>jacek.tomaka@poczta.fm</name>
</author>
<published>2018-04-23T16:14:25Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=83a951a8ed3c5c9b57d8c7a648bdcf7bc2ae881c'/>
<id>urn:sha1:83a951a8ed3c5c9b57d8c7a648bdcf7bc2ae881c</id>
<content type='text'>
[ Upstream commit b837913fc2d9061bf9b8c0dd6bf2d24e2f98b84a ]

Make kernel print the correct number of TLB entries on Intel Xeon Phi 7210
(and others)

Before:
[ 0.320005] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0
After:
[ 0.320005] Last level dTLB entries: 4KB 256, 2MB 128, 4MB 128, 1GB 16

The entries do exist in the official Intel SMD but the type column there is
incorrect (states "Cache" where it should read "TLB"), but the entries for
the values 0x6B, 0x6C and 0x6D are correctly described as 'Data TLB'.

Signed-off-by: Jacek Tomaka &lt;jacek.tomaka@poczta.fm&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Link: https://lkml.kernel.org/r/20180423161425.24366-1-jacekt@dugeo.com
Signed-off-by: Sasha Levin &lt;alexander.levin@microsoft.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>x86/MCE/AMD: Cache SMCA MISC block addresses</title>
<updated>2018-06-05T09:46:09Z</updated>
<author>
<name>Borislav Petkov</name>
</author>
<published>2018-05-17T08:46:26Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1415eea15edcdf86632d762f81511be6df1128f8'/>
<id>urn:sha1:1415eea15edcdf86632d762f81511be6df1128f8</id>
<content type='text'>
commit 78ce241099bb363b19dbd0245442e66c8de8f567 upstream.

... into a global, two-dimensional array and service subsequent reads from
that cache to avoid rdmsr_on_cpu() calls during CPU hotplug (IPIs with IRQs
disabled).

In addition, this fixes a KASAN slab-out-of-bounds read due to wrong usage
of the bank-&gt;blocks pointer.

Fixes: 27bd59502702 ("x86/mce/AMD: Get address from already initialized block")
Reported-by: Johannes Hirte &lt;johannes.hirte@datenkhaos.de&gt;
Tested-by: Johannes Hirte &lt;johannes.hirte@datenkhaos.de&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Yazen Ghannam &lt;yazen.ghannam@amd.com&gt;
Link: http://lkml.kernel.org/r/20180414004230.GA2033@probook
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>x86/mce/AMD: Carve out SMCA get_block_address() code</title>
<updated>2018-06-05T09:46:09Z</updated>
<author>
<name>Yazen Ghannam</name>
</author>
<published>2018-02-21T10:19:00Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=75b38053ae030775f94b2a55b044c2aa88f4c642'/>
<id>urn:sha1:75b38053ae030775f94b2a55b044c2aa88f4c642</id>
<content type='text'>
commit 8a331f4a0863bea758561c921b94b4d28f7c4029 upstream.

Carve out the SMCA code in get_block_address() into a separate helper
function.

No functional change.

Signed-off-by: Yazen Ghannam &lt;yazen.ghannam@amd.com&gt;
[ Save an indentation level. ]
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Tony Luck &lt;tony.luck@intel.com&gt;
Cc: linux-edac &lt;linux-edac@vger.kernel.org&gt;
Link: http://lkml.kernel.org/r/20180215210943.11530-4-Yazen.Ghannam@amd.com
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>x86/bugs: Rename SSBD_NO to SSB_NO</title>
<updated>2018-05-22T16:56:31Z</updated>
<author>
<name>Konrad Rzeszutek Wilk</name>
</author>
<published>2018-05-17T03:18:09Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=677af592349708498671b0d9290912acb2f203e4'/>
<id>urn:sha1:677af592349708498671b0d9290912acb2f203e4</id>
<content type='text'>
commit 240da953fcc6a9008c92fae5b1f727ee5ed167ab upstream

The "336996 Speculative Execution Side Channel Mitigations" from
May defines this as SSB_NO, hence lets sync-up.

Signed-off-by: Konrad Rzeszutek Wilk &lt;konrad.wilk@oracle.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>KVM: SVM: Implement VIRT_SPEC_CTRL support for SSBD</title>
<updated>2018-05-22T16:56:31Z</updated>
<author>
<name>Tom Lendacky</name>
</author>
<published>2018-05-10T20:06:39Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7445962ff2d652bb957722ca1a08a92d09f3e5d7'/>
<id>urn:sha1:7445962ff2d652bb957722ca1a08a92d09f3e5d7</id>
<content type='text'>
commit bc226f07dcd3c9ef0b7f6236fe356ea4a9cb4769 upstream

Expose the new virtualized architectural mechanism, VIRT_SSBD, for using
speculative store bypass disable (SSBD) under SVM.  This will allow guests
to use SSBD on hardware that uses non-architectural mechanisms for enabling
SSBD.

[ tglx: Folded the migration fixup from Paolo Bonzini ]

Signed-off-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>x86/speculation, KVM: Implement support for VIRT_SPEC_CTRL/LS_CFG</title>
<updated>2018-05-22T16:56:31Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2018-05-10T18:42:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=95271aeb93d4681c65e2f94969b23ef6070367a6'/>
<id>urn:sha1:95271aeb93d4681c65e2f94969b23ef6070367a6</id>
<content type='text'>
commit 47c61b3955cf712cadfc25635bf9bc174af030ea upstream

Add the necessary logic for supporting the emulated VIRT_SPEC_CTRL MSR to
x86_virt_spec_ctrl().  If either X86_FEATURE_LS_CFG_SSBD or
X86_FEATURE_VIRT_SPEC_CTRL is set then use the new guest_virt_spec_ctrl
argument to check whether the state must be modified on the host. The
update reuses speculative_store_bypass_update() so the ZEN-specific sibling
coordination can be reused.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>x86/bugs: Rework spec_ctrl base and mask logic</title>
<updated>2018-05-22T16:56:31Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2018-05-12T18:10:00Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=bd4b410bc5ea560107126a3df18e9233baaec9f3'/>
<id>urn:sha1:bd4b410bc5ea560107126a3df18e9233baaec9f3</id>
<content type='text'>
commit be6fcb5478e95bb1c91f489121238deb3abca46a upstream

x86_spec_ctrL_mask is intended to mask out bits from a MSR_SPEC_CTRL value
which are not to be modified. However the implementation is not really used
and the bitmask was inverted to make a check easier, which was removed in
"x86/bugs: Remove x86_spec_ctrl_set()"

Aside of that it is missing the STIBP bit if it is supported by the
platform, so if the mask would be used in x86_virt_spec_ctrl() then it
would prevent a guest from setting STIBP.

Add the STIBP bit if supported and use the mask in x86_virt_spec_ctrl() to
sanitize the value which is supplied by the guest.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Borislav Petkov &lt;bp@suse.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>x86/bugs: Remove x86_spec_ctrl_set()</title>
<updated>2018-05-22T16:56:31Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2018-05-12T18:53:14Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=dde9807143e7580c3832858f62001742011da264'/>
<id>urn:sha1:dde9807143e7580c3832858f62001742011da264</id>
<content type='text'>
commit 4b59bdb569453a60b752b274ca61f009e37f4dae upstream

x86_spec_ctrl_set() is only used in bugs.c and the extra mask checks there
provide no real value as both call sites can just write x86_spec_ctrl_base
to MSR_SPEC_CTRL. x86_spec_ctrl_base is valid and does not need any extra
masking or checking.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Konrad Rzeszutek Wilk &lt;konrad.wilk@oracle.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
</feed>
