kernel.git/arch/x86/kernel/cpu/tsx.c, branch linux-rolling-stable

x86/tsx: Get the tsx= command line parameter with early_param()

2025-10-24T16:35:17Z

Use early_param() to get the value of the tsx= command line parameter. It is an early parameter, because it must be parsed before tsx_init(), which is called long before kernel_init(), where normal parameters are parsed. Although cmdline_find_option() from tsx_init() works fine, the option is later reported as unknown and passed to user space. The latter is not a real issue, but the former is confusing and makes people wonder if the tsx= parameter had any effect and double-check for typos unnecessarily. The behavior changes slightly if "tsx" is given without any argument (which is invalid syntax). Until now, the kernel logged an error message and disabled TSX. Now, the kernel still issues a warning (Malformed early option 'tsx'), but TSX state is unchanged. The new behavior is consistent with other parameters, e.g. "tsx_async_abort". [ bp: Fixup minor formatting request during review. ] Suggested-by: Pawan Gupta Signed-off-by: Petr Tesarik Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/all/cover.1758906115.git.ptesarik@suse.com

x86/tsx: Make tsx_ctrl_state static

2025-10-24T16:24:42Z

Move all definitions related to tsx_ctrl_state to tsx.c. They are never referenced outside this file. No functional change. Signed-off-by: Petr Tesarik Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Nikolay Borisov Link: https://lore.kernel.org/all/cover.1758906115.git.ptesarik@suse.com

x86/msr: Add explicit includes of

2025-05-02T08:23:47Z

For historic reasons there are some TSC-related functions in the header, even though there's an header. To facilitate the relocation of rdtsc{,_ordered}() from to and to eventually eliminate the inclusion of in , add an explicit dependency to the source files that reference definitions from . [ mingo: Clarified the changelog. ] Signed-off-by: Xin Li (Intel) Signed-off-by: Ingo Molnar Acked-by: Dave Hansen Acked-by: Peter Zijlstra (Intel) Acked-by: Ilpo Järvinen Cc: Andy Lutomirski Cc: Brian Gerst Cc: Juergen Gross Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Kees Cook Cc: Peter Zijlstra Cc: Borislav Petkov Cc: Thomas Gleixner Cc: Josh Poimboeuf Cc: Uros Bizjak Link: https://lore.kernel.org/r/20250501054241.1245648-1-xin@zytor.com

x86/msr: Rename 'wrmsrl()' to 'wrmsrq()'

2025-04-10T09:58:33Z

Suggested-by: "H. Peter Anvin" Signed-off-by: Ingo Molnar Acked-by: Peter Zijlstra (Intel) Cc: Juergen Gross Cc: Dave Hansen Cc: Xin Li Cc: Linus Torvalds

x86/msr: Rename 'rdmsrl()' to 'rdmsrq()'

2025-04-10T09:58:27Z

Suggested-by: "H. Peter Anvin" Signed-off-by: Ingo Molnar Acked-by: Peter Zijlstra (Intel) Cc: Juergen Gross Cc: Dave Hansen Cc: Xin Li Cc: Linus Torvalds

x86/cpu: Remove redundant extern x86_read_arch_cap_msr()

2023-01-10T11:40:24Z

The prototype for the x86_read_arch_cap_msr() function has moved to arch/x86/include/asm/cpu.h - kill the redundant definition in arch/x86/kernel/cpu.h and include the header. Signed-off-by: Ashok Raj Signed-off-by: Ingo Molnar Reviewed-by: Daniel Sneddon Link: https://lore.kernel.org/r/20221128172451.792595-1-ashok.raj@intel.com

x86/tsx: Add a feature bit for TSX control MSR support

2022-11-21T13:08:20Z

Support for the TSX control MSR is enumerated in MSR_IA32_ARCH_CAPABILITIES. This is different from how other CPU features are enumerated i.e. via CPUID. Currently, a call to tsx_ctrl_is_supported() is required for enumerating the feature. In the absence of a feature bit for TSX control, any code that relies on checking feature bits directly will not work. In preparation for adding a feature bit check in MSR save/restore during suspend/resume, set a new feature bit X86_FEATURE_TSX_CTRL when MSR_IA32_TSX_CTRL is present. Also make tsx_ctrl_is_supported() use the new feature bit to avoid any overhead of reading the MSR. [ bp: Remove tsx_ctrl_is_supported(), add room for two more feature bits in word 11 which are coming up in the next merge window. ] Suggested-by: Andrew Cooper Signed-off-by: Pawan Gupta Signed-off-by: Borislav Petkov Reviewed-by: Dave Hansen Cc: Link: https://lore.kernel.org/r/de619764e1d98afbb7a5fa58424f1278ede37b45.1668539735.git.pawan.kumar.gupta@linux.intel.com

x86/tsx: Disable TSX development mode at boot

2022-04-11T07:58:40Z

A microcode update on some Intel processors causes all TSX transactions to always abort by default[*]. Microcode also added functionality to re-enable TSX for development purposes. With this microcode loaded, if tsx=on was passed on the cmdline, and TSX development mode was already enabled before the kernel boot, it may make the system vulnerable to TSX Asynchronous Abort (TAA). To be on safer side, unconditionally disable TSX development mode during boot. If a viable use case appears, this can be revisited later. [*]: Intel TSX Disable Update for Selected Processors, doc ID: 643557 [ bp: Drop unstable web link, massage heavily. ] Suggested-by: Andrew Cooper Suggested-by: Borislav Petkov Signed-off-by: Pawan Gupta Signed-off-by: Borislav Petkov Tested-by: Neelima Krishnan Cc: Link: https://lore.kernel.org/r/347bd844da3a333a9793c6687d4e4eb3b2419a3e.1646943780.git.pawan.kumar.gupta@linux.intel.com

x86/tsx: Use MSR_TSX_CTRL to clear CPUID bits

2022-04-11T07:54:34Z

tsx_clear_cpuid() uses MSR_TSX_FORCE_ABORT to clear CPUID.RTM and CPUID.HLE. Not all CPUs support MSR_TSX_FORCE_ABORT, alternatively use MSR_IA32_TSX_CTRL when supported. [ bp: Document how and why TSX gets disabled. ] Fixes: 293649307ef9 ("x86/tsx: Clear CPUID bits when TSX always force aborts") Reported-by: kernel test robot Signed-off-by: Pawan Gupta Signed-off-by: Borislav Petkov Tested-by: Neelima Krishnan Cc: Link: https://lore.kernel.org/r/5b323e77e251a9c8bcdda498c5cc0095be1e1d3c.1646943780.git.pawan.kumar.gupta@linux.intel.com

x86/tsx: Clear CPUID bits when TSX always force aborts

2021-06-15T15:46:48Z

As a result of TSX deprecation, some processors always abort TSX transactions by default after a microcode update. When TSX feature cannot be used it is better to hide it. Clear CPUID.RTM and CPUID.HLE bits when TSX transactions always abort. [ bp: Massage commit message and comments. ] Signed-off-by: Pawan Gupta Signed-off-by: Borislav Petkov Reviewed-by: Thomas Gleixner Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Tested-by: Neelima Krishnan Link: https://lkml.kernel.org/r/5209b3d72ffe5bd3cafdcc803f5b883f785329c3.1623704845.git-series.pawan.kumar.gupta@linux.intel.com