kernel.git/arch/x86/kernel/cpu/mce/intel.c, branch linux-5.6.y

x86/mce: Fix logic and comments around MSR_PPIN_CTL

2020-02-27T20:36:42Z

There are two implemented bits in the PPIN_CTL MSR: Bit 0: LockOut (R/WO) Set 1 to prevent further writes to MSR_PPIN_CTL. Bit 1: Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible using RDMSR. If 0, an attempt to read MSR_PPIN will cause #GP. So there are four defined values: 0: PPIN is disabled, PPIN_CTL may be updated 1: PPIN is disabled. PPIN_CTL is locked against updates 2: PPIN is enabled. PPIN_CTL may be updated 3: PPIN is enabled. PPIN_CTL is locked against updates Code would only enable the X86_FEATURE_INTEL_PPIN feature for case "2". When it should have done so for both case "2" and case "3". Fix the final test to just check for the enable bit. Also fix some of the other comments in this function. Fixes: 3f5a7896a509 ("x86/mce: Include the PPIN in MCE records when available") Signed-off-by: Tony Luck Signed-off-by: Borislav Petkov Cc: Link: https://lkml.kernel.org/r/20200226011737.9958-1-tony.luck@intel.com

x86/mce: WARN once if IA32_FEAT_CTL MSR is left unlocked

2020-01-13T16:47:18Z

WARN if the IA32_FEAT_CTL MSR is somehow left unlocked now that CPU initialization unconditionally locks the MSR. Signed-off-by: Sean Christopherson Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20191221044513.21680-6-sean.j.christopherson@intel.com

x86/msr-index: Clean up bit defines for IA32_FEATURE_CONTROL MSR

2020-01-13T16:23:08Z

As pointed out by Boris, the defines for bits in IA32_FEATURE_CONTROL are quite a mouthful, especially the VMX bits which must differentiate between enabling VMX inside and outside SMX (TXT) operation. Rename the MSR and its bit defines to abbreviate FEATURE_CONTROL as FEAT_CTL to make them a little friendlier on the eyes. Arguably, the MSR itself should keep the full IA32_FEATURE_CONTROL name to match Intel's SDM, but a future patch will add a dedicated Kconfig, file and functions for the MSR. Using the full name for those assets is rather unwieldy, so bite the bullet and use IA32_FEAT_CTL so that its nomenclature is consistent throughout the kernel. Opportunistically, fix a few other annoyances with the defines: - Relocate the bit defines so that they immediately follow the MSR define, e.g. aren't mistaken as belonging to MISC_FEATURE_CONTROL. - Add whitespace around the block of feature control defines to make it clear they're all related. - Use BIT() instead of manually encoding the bit shift. - Use "VMX" instead of "VMXON" to match the SDM. - Append "_ENABLED" to the LMCE (Local Machine Check Exception) bit to be consistent with the kernel's verbiage used for all other feature control bits. Note, the SDM refers to the LMCE bit as LMCE_ON, likely to differentiate it from IA32_MCG_EXT_CTL.LMCE_EN. Ignore the (literal) one-off usage of _ON, the SDM is simply "wrong". Signed-off-by: Sean Christopherson Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20191221044513.21680-2-sean.j.christopherson@intel.com

x86/mce: Add Xeon Icelake to list of CPUs that support PPIN

2019-11-01T16:29:36Z

New CPU model, same MSRs to control and read the inventory number. Signed-off-by: Tony Luck Signed-off-by: Borislav Petkov Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: linux-edac Cc: Thomas Gleixner Cc: x86-ml Link: https://lkml.kernel.org/r/20191028163719.19708-1-tony.luck@intel.com

x86/mce: Add Zhaoxin LMCE support

2019-10-01T10:33:33Z

Newer Zhaoxin CPUs support LMCE compatible with Intel. Add support for that. [ bp: Export functions and massage. ] Signed-off-by: Tony W Wang-oc Signed-off-by: Borislav Petkov Cc: CooperYan@zhaoxin.com Cc: DavidWang@zhaoxin.com Cc: HerryYang@zhaoxin.com Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: linux-edac Cc: QiyuanWang@zhaoxin.com Cc: Thomas Gleixner Cc: Tony Luck Cc: x86-ml Link: https://lkml.kernel.org/r/1568787573-1297-5-git-send-email-TonyWWang-oc@zhaoxin.com

x86/mce: Add Zhaoxin CMCI support

2019-10-01T10:33:09Z

All newer Zhaoxin CPUs support CMCI and are compatible with Intel's Machine-Check Architecture. Add that support for Zhaoxin CPUs. [ bp: Massage comments and export intel_init_cmci(). ] Signed-off-by: Tony W Wang-oc Signed-off-by: Borislav Petkov Cc: CooperYan@zhaoxin.com Cc: DavidWang@zhaoxin.com Cc: HerryYang@zhaoxin.com Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: linux-edac Cc: QiyuanWang@zhaoxin.com Cc: Thomas Gleixner Cc: Tony Luck Cc: x86-ml Link: https://lkml.kernel.org/r/1568787573-1297-4-git-send-email-TonyWWang-oc@zhaoxin.com

x86/intel: Aggregate microserver naming

2019-08-28T09:29:32Z

Currently big microservers have _XEON_D while small microservers have _X, Make it uniformly: _D. for i in `git grep -l "$INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6$.*_$X\|XEON_D$"` do sed -i -e 's/$\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6$.*ATOM.*\)_X/\1_D/g' \ -e 's/$\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6$.*\)_XEON_D/\1_D/g' ${i} done Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Tony Luck Cc: x86@kernel.org Cc: Dave Hansen Cc: Thomas Gleixner Cc: Borislav Petkov Link: https://lkml.kernel.org/r/20190827195122.677152989@infradead.org

x86/mce: Streamline MCE subsystem's naming

2018-12-05T17:00:29Z