kernel.git/arch/x86/kernel/amd_nb.c, branch linux-5.4.y

x86/amd_nb: Restrict init function to AMD-based systems

2025-03-13T11:43:02Z

[ Upstream commit bee9e840609cc67d0a7d82f22a2130fb7a0a766d ] The code implicitly operates on AMD-based systems by matching on PCI IDs. However, the use of these IDs is going away. Add an explicit CPU vendor check instead of relying on PCI IDs. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20241206161210.163701-3-yazen.ghannam@amd.com Signed-off-by: Sasha Levin

x86/amd_nb: Check for invalid SMN reads

2024-07-05T07:08:25Z

[ Upstream commit c625dabbf1c4a8e77e4734014f2fde7aa9071a1f ] AMD Zen-based systems use a System Management Network (SMN) that provides access to implementation-specific registers. SMN accesses are done indirectly through an index/data pair in PCI config space. The PCI config access may fail and return an error code. This would prevent the "read" value from being updated. However, the PCI config access may succeed, but the return value may be invalid. This is in similar fashion to PCI bad reads, i.e. return all bits set. Most systems will return 0 for SMN addresses that are not accessible. This is in line with AMD convention that unavailable registers are Read-as-Zero/Writes-Ignored. However, some systems will return a "PCI Error Response" instead. This value, along with an error code of 0 from the PCI config access, will confuse callers of the amd_smn_read() function. Check for this condition, clear the return value, and set a proper error code. Fixes: ddfe43cdc0da ("x86/amd_nb: Add SMN and Indirect Data Fabric access for AMD Fam17h") Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230403164244.471141-1-yazen.ghannam@amd.com Signed-off-by: Sasha Levin

x86/amd_nb: Add AMD family 17h model 60h PCI IDs

2020-06-22T07:31:17Z

[ Upstream commit a4e91825d7e1252f7cba005f1451e5464b23c15d ] Add PCI IDs for AMD Renoir (4000-series Ryzen CPUs). This is necessary to enable support for temperature sensors via the k10temp module. Signed-off-by: Alexander Monakov Signed-off-by: Borislav Petkov Acked-by: Yazen Ghannam Acked-by: Guenter Roeck Link: https://lkml.kernel.org/r/20200510204842.2603-2-amonakov@ispras.ru Signed-off-by: Sasha Levin

x86/amd_nb: Add Family 19h PCI IDs

2020-06-22T07:31:16Z

[ Upstream commit b3f79ae45904ae987a7c06a9e8d6084d7b73e67f ] Add the new PCI Device 18h IDs for AMD Family 19h systems. Note that Family 19h systems will not have a new PCI root device ID. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20200110015651.14887-4-Yazen.Ghannam@amd.com Signed-off-by: Sasha Levin

x86/amd_nb: Add PCI device IDs for family 17h, model 70h

2019-09-03T19:47:17Z

The AMD Ryzen gen 3 processors came with a different PCI IDs for the function 3 & 4 which are used to access the SMN interface. The root PCI address however remained at the same address as the model 30h. Adding the F3/F4 PCI IDs respectively to the misc and link ids appear to be sufficient for k10temp, so let's add them and follow up on the patch if other functions need more tweaking. Vicki Pfau sent an identical patch after I checked that no-one had written this patch. I would have been happy about dropping my patch but unlike for his patch series, I had already Cc:ed the x86 people and they already reviewed the changes. Since Vicki has not answered to any email after his initial series, let's assume she is on vacation and let's avoid duplication of reviews from the maintainers and merge my series. To acknowledge Vicki's anteriority, I added her S-o-b to the patch. v2, suggested by Guenter Roeck and Brian Woods: - rename from 71h to 70h Signed-off-by: Vicki Pfau Signed-off-by: Marcel Bocu Tested-by: Marcel Bocu Acked-by: Thomas Gleixner Acked-by: Brian Woods Acked-by: Bjorn Helgaas # pci_ids.h Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: "H. Peter Anvin" Cc: x86@kernel.org Cc: "Woods, Brian" Cc: Clemens Ladisch Cc: Jean Delvare Cc: Guenter Roeck Cc: linux-hwmon@vger.kernel.org Link: https://lore.kernel.org/r/20190722174510.2179-1-marcel.p.bocu@gmail.com Signed-off-by: Guenter Roeck

Merge branch 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2019-07-09T00:27:24Z

Pull x86 cleanups from Ingo Molnar: "Misc small cleanups: removal of superfluous code and coding style cleanups mostly" * 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/kexec: Make variable static and config dependent x86/defconfigs: Remove useless UEVENT_HELPER_PATH x86/amd_nb: Make hygon_nb_misc_ids static x86/tsc: Move inline keyword to the beginning of function declarations x86/io_delay: Define IO_DELAY macros in C instead of Kconfig x86/io_delay: Break instead of fallthrough in switch statement

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 477

2019-06-19T15:09:51Z

Based on 1 normalized pattern(s): subject to gplv2 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 1 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081204.018005938@linutronix.de Signed-off-by: Greg Kroah-Hartman

x86/amd_nb: Make hygon_nb_misc_ids static

2019-06-14T18:25:58Z

Fix the following sparse warning: arch/x86/kernel/amd_nb.c:74:28: warning: symbol 'hygon_nb_misc_ids' was not declared. Should it be static? Reported-by: Hulk Robot Signed-off-by: YueHaibing Signed-off-by: Borislav Petkov Cc: Bjorn Helgaas Cc: Brian Woods Cc: Guenter Roeck Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Pu Wen Cc: Thomas Gleixner Cc: x86-ml Link: https://lkml.kernel.org/r/20190614155441.22076-1-yuehaibing@huawei.com

x86/amd_nb: Add PCI device IDs for family 17h, model 30h

2018-11-07T20:36:09Z

Add the PCI device IDs for family 17h model 30h, since they are needed for accessing various registers via the data fabric/SMN interface. Signed-off-by: Brian Woods Signed-off-by: Borislav Petkov CC: Bjorn Helgaas CC: Clemens Ladisch CC: Guenter Roeck CC: "H. Peter Anvin" CC: Ingo Molnar CC: Jean Delvare CC: Jia Zhang CC: CC: CC: Pu Wen CC: Thomas Gleixner CC: x86-ml Link: http://lkml.kernel.org/r/20181106200754.60722-4-brian.woods@amd.com

x86/amd_nb: Add support for newer PCI topologies

2018-11-07T20:28:29Z

Add support for new processors which have multiple PCI root complexes per data fabric/system management network interface. If there are (N) multiple PCI roots per DF/SMN interface, then the PCI roots are redundant (as far as SMN/DF access goes). For each DF/SMN interface: map to the first available PCI root and skip the next N-1 PCI roots so the following DF/SMN interface get mapped to a correct PCI root. Ex: DF/SMN 0 -> 60 40 20 00 DF/SMN 1 -> e0 c0 a0 80 Signed-off-by: Brian Woods Signed-off-by: Borislav Petkov CC: Bjorn Helgaas CC: Clemens Ladisch CC: Guenter Roeck CC: "H. Peter Anvin" CC: Ingo Molnar CC: Jean Delvare CC: Jia Zhang CC: CC: CC: Pu Wen CC: Thomas Gleixner CC: x86-ml Link: http://lkml.kernel.org/r/20181106200754.60722-3-brian.woods@amd.com