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<title>kernel.git/arch/x86/kernel/amd_nb.c, branch linux-3.18.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.18.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.18.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2016-07-19T22:20:16Z</updated>
<entry>
<title>x86/amd_nb: Fix boot crash on non-AMD systems</title>
<updated>2016-07-19T22:20:16Z</updated>
<author>
<name>Borislav Petkov</name>
</author>
<published>2016-06-16T17:13:49Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=82736d510a43d7362f0899f7cc61429f0b342647'/>
<id>urn:sha1:82736d510a43d7362f0899f7cc61429f0b342647</id>
<content type='text'>
[ Upstream commit 1ead852dd88779eda12cb09cc894a03d9abfe1ec ]

Fix boot crash that triggers if this driver is built into a kernel and
run on non-AMD systems.

AMD northbridges users call amd_cache_northbridges() and it returns
a negative value to signal that we weren't able to cache/detect any
northbridges on the system.

At least, it should do so as all its callers expect it to do so. But it
does return a negative value only when kmalloc() fails.

Fix it to return -ENODEV if there are no NBs cached as otherwise, amd_nb
users like amd64_edac, for example, which relies on it to know whether
it should load or not, gets loaded on systems like Intel Xeons where it
shouldn't.

Reported-and-tested-by: Tony Battersby &lt;tonyb@cybernetics.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Cc: &lt;stable@vger.kernel.org&gt;
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Link: http://lkml.kernel.org/r/1466097230-5333-2-git-send-email-bp@alien8.de
Link: https://lkml.kernel.org/r/5761BEB0.9000807@cybernetics.com
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;alexander.levin@verizon.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'edac_for_3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp</title>
<updated>2014-04-01T20:54:00Z</updated>
<author>
<name>Linus Torvalds</name>
</author>
<published>2014-04-01T20:54:00Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=62ff577fa2fec87edbf26f53e87210ba726d4d44'/>
<id>urn:sha1:62ff577fa2fec87edbf26f53e87210ba726d4d44</id>
<content type='text'>
Pull EDAC updates from Borislav Petkov:
 "A bunch of EDAC updates all over the place:

   - Support for new AMD models, along with more graceful fallback for
     unsupported hw.

   - Bunch of fixes from SUSE accumulated from bug reports

   - Misc other fixes and cleanups"

* tag 'edac_for_3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
  amd64_edac: Add support for newer F16h models
  i7core_edac: Drop unused variable
  i82875p_edac: Drop redundant call to pci_get_device()
  amd8111_edac: Fix leaks in probe error paths
  e752x_edac: Drop pvt-&gt;bridge_ck
  MCE, AMD: Fix decoding module loading on unsupported hw
  i5100_edac: Remove an unneeded condition in i5100_init_csrows()
  sb_edac: Degrade log level for device registration
  amd64_edac: Fix logic to determine channel for F15 M30h processors
  edac/85xx: Remove deprecated IRQF_DISABLED
  i3200_edac: Add a missing pci_disable_device() on the exit path
  i5400_edac: Disable device when unloading module
  e752x_edac: Simplify call to pci_get_device()
</content>
</entry>
<entry>
<title>amd64_edac: Add support for newer F16h models</title>
<updated>2014-02-27T17:03:16Z</updated>
<author>
<name>Aravind Gopalakrishnan</name>
</author>
<published>2014-02-20T16:28:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=85a8885bd0e00569108aa7b5e26b89c752e3cd51'/>
<id>urn:sha1:85a8885bd0e00569108aa7b5e26b89c752e3cd51</id>
<content type='text'>
Extend ECC decoding support for F16h M30h. Tested on F16h M30h with ECC
turned on using mce_amd_inj module and the patch works fine.

Signed-off-by: Aravind Gopalakrishnan &lt;Aravind.Gopalakrishnan@amd.com&gt;
Link: http://lkml.kernel.org/r/1392913726-16961-1-git-send-email-Aravind.Gopalakrishnan@amd.com
Tested-by: Arindam Nath &lt;Arindam.Nath@amd.com&gt;
Acked-by: H. Peter Anvin &lt;hpa@zytor.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
</content>
</entry>
<entry>
<title>x86/AMD/NB: Fix amd_set_subcaches() parameter type</title>
<updated>2014-01-25T07:50:09Z</updated>
<author>
<name>Dan Carpenter</name>
</author>
<published>2014-01-21T07:22:09Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2993ae3305ad10b41e0d0bc2662f7754ee8e30fa'/>
<id>urn:sha1:2993ae3305ad10b41e0d0bc2662f7754ee8e30fa</id>
<content type='text'>
This is under CAP_SYS_ADMIN, but Smatch complains that mask comes
from the user and the test for "mask &gt; 0xf" can underflow.

The fix is simple: amd_set_subcaches() should hand down not an 'int'
but an 'unsigned long' like it was originally indended to do.

Signed-off-by: Dan Carpenter &lt;dan.carpenter@oracle.com&gt;
Acked-by: Borislav Petkov &lt;bp@suse.de&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Daniel J Blueman &lt;daniel@numascale-asia.com&gt;
Link: http://lkml.kernel.org/r/20140121072209.GA22095@elgon.mountain
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
</content>
</entry>
<entry>
<title>x86, amd_nb: Clarify F15h, model 30h GART and L3 support</title>
<updated>2013-08-12T13:30:08Z</updated>
<author>
<name>Aravind Gopalakrishnan</name>
</author>
<published>2013-08-02T22:43:03Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7d64ac6422092adbbdaa279ab32f9d4c90a84558'/>
<id>urn:sha1:7d64ac6422092adbbdaa279ab32f9d4c90a84558</id>
<content type='text'>
F15h, models 0x30 and later don't have a GART. Note that. Also check
CPUID leaf 0x80000006 for L3 prescence because there are models which
don't sport an L3 cache.

Signed-off-by: Aravind Gopalakrishnan &lt;Aravind.Gopalakrishnan@amd.com&gt;
[ Boris: rewrite commit message, cleanup comments. ]
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
</content>
</entry>
<entry>
<title>Merge branch 'x86-ras-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2013-04-30T15:42:45Z</updated>
<author>
<name>Linus Torvalds</name>
</author>
<published>2013-04-30T15:42:45Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5a5a1bf099d6942399ea0b34a62e5f0bc4c5c36e'/>
<id>urn:sha1:5a5a1bf099d6942399ea0b34a62e5f0bc4c5c36e</id>
<content type='text'>
Pull x86 RAS changes from Ingo Molnar:

 - Add an Intel CMCI hotplug fix

 - Add AMD family 16h EDAC support

 - Make the AMD MCE banks code more flexible for virtual environments

* 'x86-ras-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  amd64_edac: Add Family 16h support
  x86/mce: Rework cmci_rediscover() to play well with CPU hotplug
  x86, MCE, AMD: Use MCG_CAP MSR to find out number of banks on AMD
  x86, MCE, AMD: Replace shared_bank array with is_shared_bank() helper
</content>
</entry>
<entry>
<title>amd64_edac: Add Family 16h support</title>
<updated>2013-04-19T10:46:50Z</updated>
<author>
<name>Aravind Gopalakrishnan</name>
</author>
<published>2013-04-17T19:57:13Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=94c1acf2c85b03a59a42d931a94a13a76c123a62'/>
<id>urn:sha1:94c1acf2c85b03a59a42d931a94a13a76c123a62</id>
<content type='text'>
Add code to handle DRAM ECC errors decoding for Fam16h.

Tested on Fam16h with ECC turned on using the mce_amd_inj facility and
works fine.

Signed-off-by: Aravind Gopalakrishnan &lt;Aravind.Gopalakrishnan@amd.com&gt;
[ Boris: cleanups and clarifications ]
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
</content>
</entry>
<entry>
<title>x86: Constify a few items</title>
<updated>2013-03-11T14:11:03Z</updated>
<author>
<name>Jan Beulich</name>
</author>
<published>2013-03-11T09:56:05Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c391c7884633cdc317a60fbf152d1764282fe633'/>
<id>urn:sha1:c391c7884633cdc317a60fbf152d1764282fe633</id>
<content type='text'>
This in particular re-does the compiler warning fix 9faec5b
("perf/x86: Fix P6 driver section warning"), tightening the
section attributes rather than relaxing them.

Signed-off-by: Jan Beulich &lt;jbeulich@suse.com&gt;
Cc: Shaun Ruffell &lt;sruffell@digium.com&gt;
Cc: yangyongqiang &lt;yangyongqiang01@baidu.com&gt;
Cc: Cyrill Gorcunov &lt;gorcunov@gmail.com&gt;
Cc: Vince Weaver &lt;vincent.weaver@maine.edu&gt;
Link: http://lkml.kernel.org/r/513DB84502000078000C4880@nat28.tlf.novell.com
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'x86-mce-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2012-07-22T23:07:45Z</updated>
<author>
<name>Linus Torvalds</name>
</author>
<published>2012-07-22T23:07:45Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5b160bd426946c85f32b15e5d34d62d2618a5a87'/>
<id>urn:sha1:5b160bd426946c85f32b15e5d34d62d2618a5a87</id>
<content type='text'>
Pull x86/mce changes from Ingo Molnar:
 "This tree improves the AMD thresholding bank code and includes a
  memory fault signal handling fixlet."

* 'x86-mce-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mce: Fix siginfo_t-&gt;si_addr value for non-recoverable memory faults
  x86, MCE, AMD: Update copyrights and boilerplate
  x86, MCE, AMD: Give proper names to the thresholding banks
  x86, MCE, AMD: Make error_count read only
  x86, MCE, AMD: Cleanup reading of error_count
  x86, MCE, AMD: Print decimal thresholding values
  x86, MCE, AMD: Move shared bank to node descriptor
  x86, MCE, AMD: Remove local_allocate_... wrapper
  x86, MCE, AMD: Remove shared banks sysfs linking
  x86, amd_nb: Export model 0x10 and later PCI id
</content>
</entry>
<entry>
<title>x86, amd_nb: Export model 0x10 and later PCI id</title>
<updated>2012-06-07T10:43:41Z</updated>
<author>
<name>Borislav Petkov</name>
</author>
<published>2012-05-04T16:28:21Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=24214449b00b94328e239d3c35cda3e6fe0f931b'/>
<id>urn:sha1:24214449b00b94328e239d3c35cda3e6fe0f931b</id>
<content type='text'>
Add the F3 PCI id of F15h, model 0x10 to pci_ids.h and to the amd_nb
code which generates the list of northbridges on an AMD box. Shorten
define name while at it so that it fits into pci_ids.h.

Acked-by: Clemens Ladisch &lt;clemens@ladisch.de&gt;
Cc: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Andreas Herrmann &lt;andreas.herrmann3@amd.com&gt;
Signed-off-by: Borislav Petkov &lt;borislav.petkov@amd.com&gt;
</content>
</entry>
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