kernel.git/arch/x86/kernel/acpi/cppc.c, branch linux-5.18.y

ACPI: CPPC: Fix enabling CPPC on AMD systems with shared memory

2022-07-22T08:21:57Z

commit fbd74d16890b9f5d08ea69b5282b123c894f8860 upstream. When commit 72f2ecb7ece7 ("ACPI: bus: Set CPPC _OSC bits for all and when CPPC_LIB is supported") was introduced, we found collateral damage that a number of AMD systems that supported CPPC but didn't advertise support in _OSC stopped having a functional amd-pstate driver. The _OSC was only enforced on Intel systems at that time. This was fixed for the MSR based designs by commit 8b356e536e69f ("ACPI: CPPC: Don't require _OSC if X86_FEATURE_CPPC is supported") but some shared memory based designs also support CPPC but haven't advertised support in the _OSC. Add support for those designs as well by hardcoding the list of systems. Fixes: 72f2ecb7ece7 ("ACPI: bus: Set CPPC _OSC bits for all and when CPPC_LIB is supported") Fixes: 8b356e536e69f ("ACPI: CPPC: Don't require _OSC if X86_FEATURE_CPPC is supported") Link: https://lore.kernel.org/all/3559249.JlDtxWtqDm@natalenko.name/ Cc: 5.18+ # 5.18+ Reported-and-tested-by: Oleksandr Natalenko Signed-off-by: Mario Limonciello Signed-off-by: Rafael J. Wysocki Signed-off-by: Greg Kroah-Hartman

ACPI: CPPC: Don't require _OSC if X86_FEATURE_CPPC is supported

2022-07-12T14:42:23Z

[ Upstream commit 8b356e536e69f3a4d6778ae9f0858a1beadabb1f ] commit 72f2ecb7ece7 ("ACPI: bus: Set CPPC _OSC bits for all and when CPPC_LIB is supported") added support for claiming to support CPPC in _OSC on non-Intel platforms. This unfortunately caused a regression on a vartiety of AMD platforms in the field because a number of AMD platforms don't set the `_OSC` bit 5 or 6 to indicate CPPC or CPPC v2 support. As these AMD platforms already claim CPPC support via a dedicated MSR from `X86_FEATURE_CPPC`, use this enable this feature rather than requiring the `_OSC` on platforms with a dedicated MSR. If there is additional breakage on the shared memory designs also missing this _OSC, additional follow up changes may be needed. Fixes: 72f2ecb7ece7 ("Set CPPC _OSC bits for all and when CPPC_LIB is supported") Reported-by: Perry Yuan Signed-off-by: Mario Limonciello Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin

x86/ACPI: CPPC: Move init_freq_invariance_cppc() into x86 CPPC

2022-03-08T18:16:43Z

The init_freq_invariance_cppc code actually doesn't need the SMP functionality. So setting the CONFIG_SMP as the check condition for init_freq_invariance_cppc may cause the confusion to misunderstand the CPPC. And the x86 CPPC file is better space to store the CPPC related functions, while the init_freq_invariance_cppc is out of smpboot, that means, the CONFIG_SMP won't be mandatory condition any more. And It's more clear than before. Signed-off-by: Huang Rui [ rjw: Subject adjustment ] Signed-off-by: Rafael J. Wysocki

x86/ACPI: CPPC: Move AMD maximum frequency ratio setting function into x86 CPPC

2022-03-08T18:16:43Z

The AMD maximum frequency ratio setting function depends on CPPC, so the x86 CPPC implementation file is better space for this function. Signed-off-by: Huang Rui [ rjw: Subject adjustment ] Signed-off-by: Rafael J. Wysocki

x86/ACPI: CPPC: Rename cppc_msr.c to cppc.c

2022-03-08T18:16:43Z

Rename the cppc_msr.c to cppc.c in x86 ACPI, that expects to use this file to cover more function implementation for ACPI CPPC beside MSR helpers. Naming as "cppc" is more straightforward as one of the functionalities under ACPI subsystem. Signed-off-by: Huang Rui [ rjw: Subject ] Signed-off-by: Rafael J. Wysocki