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<title>kernel.git/arch/x86/include/asm/cacheinfo.h, branch linux-4.19.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.19.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.19.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2018-05-06T10:49:15Z</updated>
<entry>
<title>x86/CPU/AMD: Calculate last level cache ID from number of sharing threads</title>
<updated>2018-05-06T10:49:15Z</updated>
<author>
<name>Suravee Suthikulpanit</name>
</author>
<published>2018-04-27T21:34:37Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=68091ee7ac3c1a8786fe1bebbd616b14236efb99'/>
<id>urn:sha1:68091ee7ac3c1a8786fe1bebbd616b14236efb99</id>
<content type='text'>
Last Level Cache ID can be calculated from the number of threads sharing
the cache, which is available from CPUID Fn0x8000001D (Cache Properties).
This is used to left-shift the APIC ID to derive LLC ID.

Therefore, default to this method unless the APIC ID enumeration does not
follow the scheme.

Signed-off-by: Suravee Suthikulpanit &lt;suravee.suthikulpanit@amd.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Link: http://lkml.kernel.org/r/1524864877-111962-5-git-send-email-suravee.suthikulpanit@amd.com

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