kernel.git/arch/x86/crypto, branch linux-2.6.30.y

crypto: aes-ni - Fix cbc mode IV saving

2009-07-02T23:50:19Z

commit e6efaa025384f86a18814a6b9f4e5d54484ab9ff upstream. Original implementation of aesni_cbc_dec do not save IV if input length % 4 == 0. This will make decryption of next block failed. Signed-off-by: Huang Ying Signed-off-by: Herbert Xu Signed-off-by: Greg Kroah-Hartman

crypto: aes-ni - Add support to Intel AES-NI instructions for x86_64 platform

2009-02-18T08:48:06Z

Intel AES-NI is a new set of Single Instruction Multiple Data (SIMD) instructions that are going to be introduced in the next generation of Intel processor, as of 2009. These instructions enable fast and secure data encryption and decryption, using the Advanced Encryption Standard (AES), defined by FIPS Publication number 197. The architecture introduces six instructions that offer full hardware support for AES. Four of them support high performance data encryption and decryption, and the other two instructions support the AES key expansion procedure. The white paper can be downloaded from: http://softwarecommunity.intel.com/isn/downloads/intelavx/AES-Instructions-Set_WP.pdf AES may be used in soft_irq context, but MMX/SSE context can not be touched safely in soft_irq context. So in_interrupt() is checked, if in IRQ or soft_irq context, the general x86_64 implementation are used instead. Signed-off-by: Huang Ying Signed-off-by: Herbert Xu

crypto: aes - Export x86 AES encrypt/decrypt functions

2009-02-18T08:48:05Z

Intel AES-NI AES acceleration instructions touch XMM state, to use that in soft_irq context, general x86 AES implementation is used as fallback. The first parameter is changed from struct crypto_tfm * to struct crypto_aes_ctx * to make it easier to deal with 16 bytes alignment requirement of AES-NI implementation. Signed-off-by: Huang Ying Signed-off-by: Herbert Xu

crypto: aes - Move key_length in struct crypto_aes_ctx to be the last field

2009-02-18T08:48:04Z

The Intel AES-NI AES acceleration instructions need key_enc, key_dec in struct crypto_aes_ctx to be 16 byte aligned, it make this easier to move key_length to be the last one. Signed-off-by: Huang Ying Signed-off-by: Herbert Xu

crypto: crc32c-intel - Switch to shash

2008-12-25T00:01:37Z

This patch changes crc32c-intel to the new shash interface. Signed-off-by: Herbert Xu

crypto: crc32c-intel - Update copyright head

2008-12-25T00:01:18Z

The original copyright head for crc32c-intel.c is incorrect. Please merge the patch to update it. Signed-Off-By: Kent Liu Signed-off-by: Herbert Xu

crypto: crc32c - Use Intel CRC32 instruction

2008-08-29T05:49:50Z

From NHM processor onward, Intel processors can support hardware accelerated CRC32c algorithm with the new CRC32 instruction in SSE 4.2 instruction set. The patch detects the availability of the feature, and chooses the most proper way to calculate CRC32c checksum. Byte code instructions are used for compiler compatibility. No MMX / XMM registers is involved in the implementation. Signed-off-by: Austin Zhang Signed-off-by: Kent Liu Signed-off-by: Herbert Xu

[CRYPTO] aes-x86-32: Remove unused return code

2008-04-21T02:19:21Z

The return parameter isn't used remove it. Signed-off-by: Sebastian Siewior Signed-off-by: Herbert Xu

[CRYPTO] twofish: Merge common glue code

2008-01-14T06:07:57Z

There is almost no difference between 32 & 64 bit glue code. Signed-off-by: Sebastian Siewior Signed-off-by: Herbert Xu

[CRYPTO] salsa20: Add x86-64 assembly version

2008-01-10T21:16:57Z

This is the x86-64 version of the Salsa20 stream cipher algorithm. The original assembly code came from . It has been reformatted for clarity. Signed-off-by: Tan Swee Heng Signed-off-by: Herbert Xu