kernel.git/arch/tile/include/asm/io.h, branch linux-3.19.y

Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile

2014-12-16T21:54:16Z

Pull arch/tile updates from Chris Metcalf: "Note that one of the changes converts my old cmetcalf@tilera.com email in MAINTAINERS to the cmetcalf@ezchip.com email that you see on this email" * git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: arch/tile: update MAINTAINERS email to EZchip tile: avoid undefined behavior with regs[TREG_TP] etc arch: tile: kernel: kgdb.c: Use memcpy() instead of pointer copy one by one tile: Use the more common pr_warn instead of pr_warning arch: tile: gxio: Export symbols for module using in 'mpipe.c' arch: tile: kernel: signal.c: Use __copy_from/to_user() instead of __get/put_user()

tile: Use the more common pr_warn instead of pr_warning

2014-11-11T20:51:42Z

And other message logging neatening. Other miscellanea: o coalesce formats o realign arguments o standardize a couple of macros o use __func__ instead of embedding the function name Signed-off-by: Joe Perches Signed-off-by: Chris Metcalf

tile: io: implement dummy relaxed accessor macros for writes

2014-10-20T17:49:18Z

write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to tile, in the same vein as the dummy definitions for the relaxed read accessors. Acked-by: Chris Metcalf Signed-off-by: Will Deacon

tile: fix some -Wsign-compare warnings

2013-08-30T15:56:50Z

Normally the build doesn't include these warnings, but at one point I built with -Wsign-compare, and noticed a few things that are technically bugs. This change fixes those things. Signed-off-by: Chris Metcalf

tile PCI RC: support I/O space access

2013-08-06T16:55:32Z

To enable this functionality, configure CONFIG_TILE_PCI_IO. Without this flag, the kernel still assigns I/O address ranges to the devices, but no TRIO resource and mapping support is provided. We assign disjoint I/O address ranges to separate PCIe domains. Signed-off-by: Chris Metcalf

tile: fix memcpy_*io functions for allnoconfig

2013-02-08T18:20:40Z

On tilepro without CONFIG_PCI, we can't provide inlines of these functions, as we don't have readl/writel. In addition, fix memset_io() signature to take a volatile void *. Signed-off-by: Chris Metcalf

arch/tile: support MMIO-based readb/writeb etc.

2012-07-11T20:04:53Z

Add support for MMIO read/write on tilegx to support GXIO IORPC access. Similar to the asm-generic version, but we include memory fences on the writes to be conservative. Signed-off-by: Chris Metcalf

tile: don't panic on iomap

2011-12-04T14:00:07Z

I think panic on iomap is there just for debugging. If we return NULL instead, the generic pci_iomap will DTRT so we don't need to roll our own. Signed-off-by: Michael S. Tsirkin

arch/tile: various header improvements for building drivers

2011-05-04T18:40:54Z

This change adds a number of missing headers in asm (fb.h, parport.h, serial.h, and vga.h) using the minimal generic versions. It also adds a number of missing interfaces that showed up as build failures when trying to build various drivers not normally included in the "tile" distribution: ioremap_wc(), memset_io(), io{read,write}{16,32}be(), virt_to_bus(), bus_to_virt(), irq_canonicalize(), __pte(), __pgd(), and __pmd(). I also added a cast in virt_to_page() since not all callers pass a pointer. I fixed to properly include a __KERNEL__ guard for the __ARCH_WANT_STAT64 symbol, and to use __builtin_bswap32() even for our 64-bit architecture, since the same code is produced. I added an export for get_cycles(), since it's used in some modules. And I made properly include the __KERNEL__ guard, even though it's not yet exported, since it likely will be soon. Signed-off-by: Chris Metcalf

pci root complex: support for tile architecture

2010-11-24T18:13:49Z

This change enables PCI root complex support for TILEPro. Unlike TILE-Gx, TILEPro has no support for memory-mapped I/O, so the PCI support consists of hypervisor upcalls for PIO, DMA, etc. However, the performance is fine for the devices we have tested with so far (1Gb Ethernet, SATA, etc.). The header was tweaked to be a little bit more aggressive about disabling attempts to map/unmap IO port space. The hacky header was rolled into the header and the result was simplified. Both of the latter two headers were preliminary versions not meant for release before now - oh well. There is one quirk for our TILEmpower platform, which accidentally negotiates up to 5GT and needs to be kicked down to 2.5GT. Signed-off-by: Chris Metcalf