kernel.git/arch/sparc64/kernel/vmlinux.lds.S, branch linux-2.6.19.y

[PATCH] vmlinux.lds: consolidate initcall sections

2006-10-27T22:34:51Z

Add a vmlinux.lds.h helper macro for defining the eight-level initcall table, teach all the architectures to use it. This is a prerequisite for a patch which performs initcall synchronisation for multithreaded-probing. Cc: Greg KH Signed-off-by: Andrew Morton [ Added AVR32 as well ] Signed-off-by: Haavard Skinnemoen Signed-off-by: Linus Torvalds

[SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patch

2006-03-20T09:11:53Z

Signed-off-by: David S. Miller

[SPARC64]: Initial sun4v TLB miss handling infrastructure.

2006-03-20T09:11:52Z

Things are a little tricky because, unlike sun4u, we have to: 1) do a hypervisor trap to do the TLB load. 2) do the TSB lookup calculations by hand Signed-off-by: David S. Miller

[SPARC64]: Sanitize %pstate writes for sun4v.

2006-03-20T09:11:50Z

If we're just switching between different alternate global sets, nop it out on sun4v. Also, get rid of all of the alternate global save/restore in the OBP CIF trampoline code. Signed-off-by: David S. Miller

[SPARC64]: Add initial code to twiddle %gl on trap entry/exit.

2006-03-20T09:11:48Z

Instead of setting/clearing PSTATE_AG we have to change the %gl register value on sun4v. Signed-off-by: David S. Miller

[SPARC64]: Refine code sequences to get the cpu id.

2006-03-20T09:11:35Z

On uniprocessor, it's always zero for optimize that. On SMP, the jmpl to the stub kills the return address stack in the cpu branch prediction logic, so expand the code sequence inline and use a code patching section to fix things up. This also always better and explicit register selection, which will be taken advantage of in a future changeset. The hard_smp_processor_id() function is big, so do not inline it. Fix up tests for Jalapeno to also test for Serrano chips too. These tests want "jbus Ultra-IIIi" cases to match, so that is what we should test for. Signed-off-by: David S. Miller

[SPARC64]: Access TSB with physical addresses when possible.

2006-03-20T09:11:32Z

This way we don't need to lock the TSB into the TLB. The trick is that every TSB load/store is registered into a special instruction patch section. The default uses virtual addresses, and the patch instructions use physical address load/stores. We can't do this on all chips because only cheetah+ and later have the physical variant of the atomic quad load. Signed-off-by: David S. Miller

[SPARC64]: Increase swapper_tsb size to 32K.

2006-03-20T09:11:26Z

Signed-off-by: David S. Miller

[SPARC64]: Move away from virtual page tables, part 1.

2006-03-20T09:11:13Z

We now use the TSB hardware assist features of the UltraSPARC MMUs. SMP is currently knowingly broken, we need to find another place to store the per-cpu base pointers. We hid them away in the TSB base register, and that obviously will not work any more :-) Another known broken case is non-8KB base page size. Also noticed that flush_tlb_all() is not referenced anywhere, only the internal __flush_tlb_all() (local cpu only) is used by the sparc64 port, so we can get rid of flush_tlb_all(). The kernel gets it's own 8KB TSB (swapper_tsb) and each address space gets it's own private 8K TSB. Later we can add code to dynamically increase the size of per-process TSB as the RSS grows. An 8KB TSB is good enough for up to about a 4MB RSS, after which the TSB starts to incur many capacity and conflict misses. We even accumulate OBP translations into the kernel TSB. Another area for refinement is large page size support. We could use a secondary address space TSB to handle those. Signed-off-by: David S. Miller

[SPARC]: Use STABS_DEBUG and DWARF_DEBUG macros in vmlinux.lds.S

2005-12-28T21:22:54Z

Signed-off-by: David S. Miller