kernel.git/arch/sparc64/kernel/ttable.S, branch linux-2.6.28.y

sparc64: Convert to generic helpers for IPI function calls.

2008-07-18T06:44:50Z

Signed-off-by: David S. Miller

sparc: Add kgdb support.

2008-04-29T09:38:50Z

Current limitations: 1) On SMP single stepping has some fundamental issues, shared with other sw single-step architectures such as mips and arm. 2) On 32-bit sparc we don't support SMP kgdb yet. That requires some reworking of the IPI mechanisms and infrastructure on that platform. Signed-off-by: David S. Miller

[SPARC]: Remove SunOS and Solaris binary support.

2008-04-21T22:10:15Z

As per Documentation/feature-removal-schedule.txt Signed-off-by: David S. Miller

[SPARC64]: Unify timer interrupt handler.

2007-04-26T08:54:11Z

Things were scattered all over the place, split between SMP and non-SMP. Unify it all so that dyntick support is easier to add. Signed-off-by: David S. Miller

Remove obsolete #include

2006-06-30T17:25:36Z

Signed-off-by: Jörn Engel Signed-off-by: Adrian Bunk

[SPARC64]: Send all device interrupts via one PIL.

2006-06-20T08:20:00Z

This is the first in a series of cleanups that will hopefully allow a seamless attempt at using the generic IRQ handling infrastructure in the Linux kernel. Define PIL_DEVICE_IRQ and vector all device interrupts through there. Get rid of the ugly pil0_dummy_{bucket,desc}, instead vector the timer interrupt directly to a specific handler since the timer interrupt is the only event that will be signaled on PIL 14. The irq_worklist is now in the per-cpu trap_block[]. Signed-off-by: David S. Miller

[SPARC64]: Fix new context version SMP handling.

2006-03-20T09:14:21Z

Don't piggy back the SMP receive signal code to do the context version change handling. Instead allocate another fixed PIL number for this asynchronous cross-call. We can't use smp_call_function() because this thing is invoked with interrupts disabled and a few spinlocks held. Also, fix smp_call_function_mask() to count "cpus" correctly. There is no guarentee that the local cpu is in the mask yet that is exactly what this code was assuming. Signed-off-by: David S. Miller

[SPARC64]: Put SUN4V ITSB miss into correct trap table entry.

2006-03-20T09:13:27Z

It's 0x9 not 0xb. Signed-off-by: David S. Miller

[SPARC64]: Implement sun4v TSB miss handlers.

2006-03-20T09:12:05Z

When we register a TSB with the hypervisor, so that it or hardware can handle TLB misses and do the TSB walk for us, the hypervisor traps down to these trap when it incurs a TSB miss. Processing is simple, we load the missing virtual address and context, and do a full page table walk. Signed-off-by: David S. Miller

[SPARC64]: Sun4v interrupt handling.

2006-03-20T09:12:01Z

Sun4v has 4 interrupt queues: cpu, device, resumable errors, and non-resumable errors. A set of head/tail offset pointers help maintain a work queue in physical memory. The entries are 64-bytes in size. Each queue is allocated then registered with the hypervisor as we bring cpus up. The two error queues each get a kernel side buffer that we use to quickly empty the main interrupt queue before we call up to C code to log the event and possibly take evasive action. Signed-off-by: David S. Miller