kernel.git/arch/sparc64/kernel/process.c, branch linux-2.6.19.y

Remove obsolete #include

2006-06-30T17:25:36Z

Signed-off-by: Jörn Engel Signed-off-by: Adrian Bunk

[SPARC64]: Use sun4v_cpu_idle() in cpu_idle() on SUN4V.

2006-03-20T09:13:54Z

We have to turn off the "polling nrflag" bit when we sleep the cpu like this, so that we'll get a cross-cpu interrupt to wake the processor up from the yield. We also have to disable PSTATE_IE in %pstate around the yield call and recheck need_resched() in order to avoid any races. Signed-off-by: David S. Miller

[SPARC64]: Kill cpudata->idle_volume.

2006-03-20T09:13:51Z

Set, but never used. We used to use this for dynamic IRQ retargetting, but that code died a long time ago. Signed-off-by: David S. Miller

[SPARC64]: Disable smp_report_regs() for now.

2006-03-20T09:13:21Z

For 32 cpus and a slow console, it just wedges the machine especially with DETECT_SOFTLOCKUP enabled. Signed-off-by: David S. Miller

[SPARC64]: Refine register window trap handling.

2006-03-20T09:11:36Z

When saving and restoing trap state, do the window spill/fill handling inline so that we never trap deeper than 2 trap levels. This is important for chips like Niagara. The window fixup code is massively simplified, and many more improvements are now possible. Signed-off-by: David S. Miller

[SPARC64]: Add infrastructure for dynamic TSB sizing.

2006-03-20T09:11:17Z

This also cleans up tsb_context_switch(). The assembler routine is now __tsb_context_switch() and the former is an inline function that picks out the bits from the mm_struct and passes it into the assembler code as arguments. setup_tsb_parms() computes the locked TLB entry to map the TSB. Later when we support using the physical address quad load instructions of Cheetah+ and later, we'll simply use the physical address for the TSB register value and set the map virtual and PTE both to zero. Signed-off-by: David S. Miller

[SPARC64]: Move away from virtual page tables, part 1.

2006-03-20T09:11:13Z

We now use the TSB hardware assist features of the UltraSPARC MMUs. SMP is currently knowingly broken, we need to find another place to store the per-cpu base pointers. We hid them away in the TSB base register, and that obviously will not work any more :-) Another known broken case is non-8KB base page size. Also noticed that flush_tlb_all() is not referenced anywhere, only the internal __flush_tlb_all() (local cpu only) is used by the sparc64 port, so we can get rid of flush_tlb_all(). The kernel gets it's own 8KB TSB (swapper_tsb) and each address space gets it's own private 8K TSB. Later we can add code to dynamically increase the size of per-process TSB as the RSS grows. An 8KB TSB is good enough for up to about a 4MB RSS, after which the TSB starts to incur many capacity and conflict misses. We even accumulate OBP translations into the kernel TSB. Another area for refinement is large page size support. We could use a secondary address space TSB to handle those. Signed-off-by: David S. Miller

[SPARC64]: Fix build with CONFIG_COMPAT disabled.

2006-01-18T22:58:05Z

Based upon a report and preliminary patch from Jim Gifford. Signed-off-by: David S. Miller

[PATCH] sparc64: task_stack_page()

2006-01-12T17:08:52Z

Signed-off-by: Al Viro Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

[PATCH] sparc64: task_thread_info()

2006-01-12T17:08:52Z

Signed-off-by: Al Viro Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds