<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/sparc64/kernel/cpu.c, branch linux-2.6.28.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-2.6.28.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-2.6.28.y'/>
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<updated>2008-09-01T04:48:12Z</updated>
<entry>
<title>sparc64: Clean up CPU chip type probing code.</title>
<updated>2008-09-01T04:48:12Z</updated>
<author>
<name>David S. Miller</name>
</author>
<published>2008-09-01T04:48:12Z</published>
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<id>urn:sha1:ba4962d7a6a10c82e55c14589d4ec635bef8446f</id>
<content type='text'>
Three main things:

1) Make prober an arch initcall instead of using hard-coded invocation
   from paging_init()

2) Shrink table size, the fpu ident stuff was never used.

3) Use named struct initialized in table.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Fix sparse warnings in arch/sparc64/kernel/{cpu,setup}.c</title>
<updated>2008-03-26T04:51:40Z</updated>
<author>
<name>David S. Miller</name>
</author>
<published>2008-03-26T04:51:40Z</published>
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<id>urn:sha1:3d5ae6b69eacfac025021998d2ce159768edcfe1</id>
<content type='text'>
We create a local header file entry.h, under arch/sparc64/kernel/,
that we can use to declare routines either defined in assembler
or only invoked from assembler.  As well as other data objects
which are private to the inner sparc64 kernel arch code.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC]: Mark linux_sparc_{fpu,chips} static.</title>
<updated>2008-02-29T05:46:59Z</updated>
<author>
<name>David S. Miller</name>
</author>
<published>2008-02-29T05:46:59Z</published>
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<id>urn:sha1:c8edc89d24546c834d7f595663afd14602855c02</id>
<content type='text'>
Caught by sparse.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Do not assume sun4v chips have load-twin/store-init support.</title>
<updated>2007-08-09T00:33:45Z</updated>
<author>
<name>David S. Miller</name>
</author>
<published>2007-08-09T00:11:39Z</published>
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<id>urn:sha1:6c70b6fc7b6fc321636a014082d9e32333da1f80</id>
<content type='text'>
Check the cpu type in the OBP device tree before committing to
using the optimized Niagara memcpy and memset implementation.

If we don't recognize the cpu type, use a completely generic
version.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Fix hard-coding of cpu type output in /proc/cpuinfo on sun4v.</title>
<updated>2007-08-08T02:09:29Z</updated>
<author>
<name>David S. Miller</name>
</author>
<published>2007-08-08T02:09:29Z</published>
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<id>urn:sha1:68c9f9fd336dc7e793cecad25f8ac40ccaa7a256</id>
<content type='text'>
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>Remove obsolete #include &lt;linux/config.h&gt;</title>
<updated>2006-06-30T17:25:36Z</updated>
<author>
<name>Jörn Engel</name>
</author>
<published>2006-06-30T17:25:36Z</published>
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<id>urn:sha1:6ab3d5624e172c553004ecc862bfeac16d9d68b7</id>
<content type='text'>
Signed-off-by: Jörn Engel &lt;joern@wohnheim.fh-wedel.de&gt;
Signed-off-by: Adrian Bunk &lt;bunk@stusta.de&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: kernel/cpu.c needs asm/spitfire.h</title>
<updated>2006-03-20T09:12:05Z</updated>
<author>
<name>David S. Miller</name>
</author>
<published>2006-02-09T11:00:00Z</published>
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<id>urn:sha1:12816ab38adddc9d7e9b3315d1739655dedc7c9f</id>
<content type='text'>
For 'tlb_type'.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Detect sun4v early in boot process.</title>
<updated>2006-03-20T09:12:03Z</updated>
<author>
<name>David S. Miller</name>
</author>
<published>2006-02-09T10:52:44Z</published>
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<id>urn:sha1:d82ace7dc4073b090a55b9740700e32b9a9ae302</id>
<content type='text'>
We look for "SUNW,sun4v" in the 'compatible' property
of the root OBP device tree node.

Protect every %ver register access, to make sure it is
not touched on sun4v, as %ver is hyperprivileged there.

Lock kernel TLB entries using hypervisor calls instead of
calls into OBP.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Use ARRAY_SIZE macro</title>
<updated>2005-11-09T20:03:42Z</updated>
<author>
<name>Tobias Klauser</name>
</author>
<published>2005-11-09T20:03:42Z</published>
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<id>urn:sha1:84c1a13a30f21406f39e546684a78ebe9859e6d7</id>
<content type='text'>
Use ARRAY_SIZE macro instead of sizeof(x)/sizeof(x[0]) and remove a
duplicate of ARRAY_SIZE which is never used anyways.

Signed-off-by: Tobias Klauser &lt;tklauser@nuerscht.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Add missing IDs for newer cpus.</title>
<updated>2005-09-28T05:50:06Z</updated>
<author>
<name>David S. Miller</name>
</author>
<published>2005-09-28T05:50:06Z</published>
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<id>urn:sha1:d2212bc7db13268bef0799d9ff4b2e511c284885</id>
<content type='text'>
Also, the us3_cpufreq driver can work on Ultra-IV and IV+.
They use the SAFARI bus register to control the clock divider
just like Ultra-III and III+ do.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
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