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<title>kernel.git/arch/sh/kernel/traps_32.c, branch linux-2.6.37.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-2.6.37.y</id>
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<updated>2010-10-12T21:55:26Z</updated>
<entry>
<title>sh: wire up perf alignment and emulation faults.</title>
<updated>2010-10-12T21:55:26Z</updated>
<author>
<name>Paul Mundt</name>
</author>
<published>2010-10-12T21:55:26Z</published>
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<id>urn:sha1:ace2dc7d12693545b67f15ab8cdb3d255c937713</id>
<content type='text'>
This plugs in the alignment and emulation fault reporting for perf sw
events.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: boot kernel with SR.BL set</title>
<updated>2010-09-30T00:43:32Z</updated>
<author>
<name>Magnus Damm</name>
</author>
<published>2010-09-24T09:05:38Z</published>
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<id>urn:sha1:68a1aed7039e5a94a8e60e23fdf676738c36086a</id>
<content type='text'>
Update the SH kernel to keep SR.BL set until the VBR
register has been initialized. Useful to allow boot
of the kernel even though exceptions are pending.

Without this patch there is a window of time when
exceptions such as NMI are enabled but no exception
handlers are installed.

This patch modifies both the zImage loader and the
actual kernel to boot with BL=1, but the zImage
loader is modfied in such a way that the init_sr
value is unchanged to not break the zImage loader
provided by kexec.

Tested on sh7724 Ecovec and on the SH4AL-DSP core
included in sh7372.

Signed-off-by: Magnus Damm &lt;damm@opensource.se&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Setup boot CPU VBR early to enable early page faults.</title>
<updated>2010-02-17T03:33:22Z</updated>
<author>
<name>Paul Mundt</name>
</author>
<published>2010-02-17T03:33:22Z</published>
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<id>urn:sha1:49f3bfe9334a4cf86079d2ee1d08e674b58862a9</id>
<content type='text'>
vmemmap and the vmsplit code amongst others need to be able to take page
faults much earlier than trap_init() time, so move this in to the early
CPU initialization. VBR setup for secondary CPUs is already handled
through start_secondary(), so we only need to do this for the boot CPU.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>Merge branches 'sh/xstate', 'sh/hw-breakpoints' and 'sh/stable-updates'</title>
<updated>2010-01-13T04:02:55Z</updated>
<author>
<name>Paul Mundt</name>
</author>
<published>2010-01-13T04:02:55Z</published>
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<id>urn:sha1:644755e7867710a23e6243dcc69cfc071985f560</id>
<content type='text'>
</content>
</entry>
<entry>
<title>sh: Split out the unaligned counters and user bits.</title>
<updated>2010-01-12T07:12:25Z</updated>
<author>
<name>Paul Mundt</name>
</author>
<published>2010-01-12T07:12:25Z</published>
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<id>urn:sha1:a99eae5417a09e0be66bf574a9a79a2a7388c967</id>
<content type='text'>
This splits out the unaligned access counters and userspace bits in to
their own generic interface, which will allow them to be wired up on sh64
too.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Tidy up the sh bios VBR handling.</title>
<updated>2010-01-12T05:50:43Z</updated>
<author>
<name>Paul Mundt</name>
</author>
<published>2010-01-12T05:50:43Z</published>
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<id>urn:sha1:191d0d24b632eb69767705acded5cbf7449ad457</id>
<content type='text'>
This moves the VBR handling out of the main trap handling code and in to
the sh-bios helper code. A couple of accessors are added in order to
permit other kernel code to get at the VBR value for state save/restore
paths.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Fix up breakpoint trap handler patching on SH-2A.</title>
<updated>2010-01-05T03:44:02Z</updated>
<author>
<name>Paul Mundt</name>
</author>
<published>2010-01-05T03:44:02Z</published>
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<id>urn:sha1:c4761815ab49feca904776dec464046bc7138d3a</id>
<content type='text'>
SH-2A was referencing the old handler that no longer exists, fix it up.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Make the unaligned trap handler always obey notification levels.</title>
<updated>2009-12-14T02:46:09Z</updated>
<author>
<name>Paul Mundt</name>
</author>
<published>2009-12-14T02:46:09Z</published>
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<id>urn:sha1:1232d88a47626cad13ba82f3a9ea814820bc1c65</id>
<content type='text'>
Presently there are a couple of paths in to the alignment handler, where
only the address error path presently quiets the notificiation messages
based on the configuration settings. We carry over the notification level
tests to the default alignment handler itself incase so that they behave
uniformly.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: convert /proc/cpu/aligmnent, /proc/cpu/kernel_alignment to seq_file</title>
<updated>2009-11-30T03:02:50Z</updated>
<author>
<name>Alexey Dobriyan</name>
</author>
<published>2009-11-27T06:42:16Z</published>
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<id>urn:sha1:9a1607071c293e48b08bd703733480b1d55c7b93</id>
<content type='text'>
Signed-off-by: Alexey Dobriyan &lt;adobriyan@gmail.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Disable SCIF2 on the SH-X3 proto CPU.</title>
<updated>2009-10-18T06:13:28Z</updated>
<author>
<name>Paul Mundt</name>
</author>
<published>2009-10-18T06:13:28Z</published>
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<id>urn:sha1:15dfdddbf0c2be680d5d2fe2bbe3aad3dba3cf0e</id>
<content type='text'>
SCIF2 and the FPU exceptions happen to share vector numbers, one in
EXPEVT and the other in INTEVT. This is a violation of the interface and
should have never made it in to silicon. On top of that, the demux hack
that was added for special dispatch is rather error prone, and introduces
more problems than it solves. Kill all of it off, and just refuse to deal
with SCIF2 outright.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
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