kernel.git/arch/sh/kernel/cpu, branch linux-2.6.21.y

sh: Fix bogus regs pointer in do_IRQ().

2007-03-14T04:03:35Z

SH-3 and SH-4 were trampling the register, and SH-2 wasn't even setting it in the first place. This ended up with some rather broken behaviour in the sysrq show_regs(). Signed-off-by: Paul Mundt

sh: Fix SH-3 cache entry_mask and way_size calculation.

2007-03-12T07:15:22Z

The code for performing the calculation was only in the SH-4 probe path, move it out to the common path so the other parts get this right too. Signed-off-by: Paul Mundt

Storage class should be before const qualifier

2007-02-17T19:11:19Z

The C99 specification states in section 6.11.5: The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature. Signed-off-by: Tobias Klauser Signed-off-by: Adrian Bunk

sh: rts7751r2d board updates.

2007-02-15T09:20:52Z

This tidies up some of the rts7751r2d mess and gets it booting again. Update the defconfig, too. Signed-off-by: Masayuki Hosokawa Signed-off-by: Paul Mundt

sh: Revert TLB miss fast-path changes that broke PTEA parts.

2007-02-14T05:13:10Z

This ended up causing problems for older parts (particularly ones using PTEA). Revert this for now, it can be added back in once it's had some more testing. Signed-off-by: Paul Mundt

sh: Fixup cpu_data references for the non-boot CPUs.

2007-02-13T01:54:45Z

There are a lot of bogus cpu_data-> references that only end up working for the boot CPU, convert these to current_cpu_data to fixup SMP. Signed-off-by: Paul Mundt

sh: Use a per-cpu ASID cache.

2007-02-13T01:54:45Z

Previously this was implemented using a global cache, cache this per-CPU instead and bump up the number of context IDs to match NR_CPUS. Signed-off-by: Paul Mundt

sh: SH-DMAC compile fixes

2007-02-13T01:54:45Z

This patch does the following: - remove the make_ipr_irq stuff from dma-sh.c and replace it with a simple channel<->irq mapping table. - add DMTEx_IRQ constants for sh4 cpus - fix sh7751 DMAE irq number The SH7780 uses the same IRQs for DMA as other SH4 types, so I put the constants on top of the dma.h file. Other CPU types need to #define their own DMTEx_IRQ contants in their appropriate header. Signed-off-by: Manuel Lauss Signed-off-by: Paul Mundt

sh: add SH7760 IPR IRQ data

2007-02-13T01:54:45Z

Add SH7760 IPR IRQ data; makes 2.6.20-rc bootable again. Signed-off-by: Manuel Lauss Signed-off-by: Paul Mundt

sh: Lazy dcache writeback optimizations.

2007-02-13T01:54:44Z

This converts the lazy dcache handling to the model described in Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a bonus, this slightly cuts down on the cache flushing frequency. With that and the PTEA handling out of the way, the update_mmu_cache() implementations can be consolidated, and we no longer have to worry about which configuration the cache is in for the SH7705 case. And finally, explicitly disable the lazy writeback on SMP (SH-4A). Signed-off-by: Paul Mundt