kernel.git/arch/sh/kernel/cpu/clock-cpg.c, branch linux-2.6.34.y

sh: add sh7724 kick callback to clk_div4_table

2010-02-22T10:11:22Z

This patch adds a ->kick() callback to clk_div4_table and ties it into sh_clk_div4_set_rate(). A sh7724 specific kick function is also added that updates the KICK bit whenever div4 clocks in FRQCRA and FRQCRB have been set. Allows us to set the VPU clock. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt

sh: introduce struct clk_div4_table

2010-02-22T10:11:20Z

This patch introduces struct clk_div4_table. The structure will be used to keep div4 specific data, and is with this patch replacing the struct clk_div_mult_table pointer arg used by the sh_clk_div4_register() functions. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt

sh: clock-cpg div4 set_rate() shift fix

2010-02-22T10:11:19Z

Make sure the div4 bitfield is shifted according to the enable_bit value in sh_clk_div4_set_rate(). Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt

sh: support SIU sourcing from external clock on sh7722

2010-01-19T11:23:00Z

Implement .set_rate() for all SH "div4 clocks," .enable(), .disable(), and .set_parent() for those, that support them. This allows, among other uses, reparenting of SIU clocks to the external source, and enabling and disabling of the IrDA clock on sh7722. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt

sh: use kzalloc() for cpg clocks

2009-06-17T06:39:53Z

Convert the shared clock cpg code from bootmem to slab. Without this patch the current bootmem code triggers WARN_ON() because the slab is available. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt

sh: add enable()/disable()/set_rate() to div6 code

2009-06-11T06:12:58Z

This patch updates the div6 clock helper code to add support for enable(), disable() and set_rate() callbacks. Needed by the camera clock enabling board code on Migo-R. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt

sh: clock div6 helper code

2009-06-11T06:07:13Z

This patch adds div6 clock helper code. The div6 clocks are simply 6-bit divide-by-n modules where n is 1 to 64. Needed for vclk on sh7722, sh7723, sh7343 and sh7366. sh7724 needs this even more for vclk, fclka, fclkb, irdaclk and spuclk. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt

sh: clock div4 frequency table offset fix

2009-06-11T06:07:04Z

This patch fixes the per clock offset calculation in sh_clk_div4_register(). Without this patch the offset to the frequency table for each clock is incorrect. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt

sh: shared div4 clock code

2009-06-01T09:07:37Z

Add shared code for 4-bit divisor clocks. Processor specific code can use SH_CLK_DIV4() to initialize div4 clocks, and then use sh_clk_div4_register() for registration. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt

sh: shared mstp32 clock code

2009-06-01T09:05:37Z

Add shared 32-bit module stop bit clock support. Processor specific code can use SH_CLK_MSTP32() to initialize module stop bit clocks, and then use sh_clk_mstp32() for registration. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt