kernel.git/arch/sh/include/cpu-sh4, branch linux-2.6.34.y

SH: fix TS field shift calculation for DMA drivers

2010-04-26T07:02:09Z

CHCR_TS_HIGH_SHIFT is defined as a shift of TS high bits in CHCR register, relative to low bits. The TS_INDEX2VAL() macro has to take this into account. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt

sh: update the TLB replacement counter for entry wiring.

2010-03-26T02:37:16Z

Presently the TLB wiring code depends on MMUCR.URB for working out where to place the wired entry, but fails to take the replacment counter in to consideration. This fixes up the wiring logic and ensures that wired entries remain so. Signed-off-by: Matt Fleming Signed-off-by: Paul Mundt

sh: Flush ITLB too in PTEAEX's flush_tlb_page()

2010-03-23T04:36:15Z

flush_tlb_page() can be used to flush TLB entries that map executable pages. Therefore, we need to ensure that the ITLB is also flushed in local_flush_tlb_page(). Signed-off-by: Matt Fleming Signed-off-by: Paul Mundt

sh: Add watch-dog register address for SH7722/SH7723/SH7724

2010-03-23T04:19:36Z

Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt

sh: merge sh7722 and sh7724 DMA register definitions

2010-03-02T02:10:52Z

DMA CHCR register layout is equal on sh7722 and sh7724, reuse definitions. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt

dmaengine: shdma: separate DMA headers.

2010-03-02T02:09:04Z

Separate SH DMA headers into ones, commonly used by both drivers, and ones, specific to each of them. This will make the future development of the dmaengine driver easier. Signed-off-by: Guennadi Liakhovetski Acked-by: Mark Brown Signed-off-by: Paul Mundt

sh: Fix up more 64-bit pgprot truncation on SH-X2 TLB.

2010-02-17T04:23:00Z

Both the store queue API and the PMB remapping take unsigned long for their pgprot flags, which cuts off the extended protection bits. In the case of the PMB this isn't really a problem since the cache attribute bits that we care about are all in the lower 32-bits, but we do it just to be safe. The store queue remapping on the other hand depends on the extended prot bits for enabling userspace access to the mappings. Signed-off-by: Paul Mundt

Merge branch 'sh/dmaengine'

2010-02-08T02:34:03Z

Conflicts: arch/sh/drivers/dma/dma-sh.c

sh: implement DMA_SLAVE capability in SH dmaengine driver

2010-02-08T00:40:26Z

Tested to work with a SIU ASoC driver on sh7722 (migor). Signed-off-by: Guennadi Liakhovetski Acked-by: Dan Williams Signed-off-by: Paul Mundt

sh: fix Transfer Size calculation in both DMA drivers

2010-02-08T00:40:24Z

Both the original arch/sh/drivers/dma/dma-sh.c and the new SH dmaengine drivers do not take into account bits 3:2 of the Transfer Size field in the CHCR register, besides, bit-field defines set bit 2, but the mask only passes bits 1:0 through. TS_16BLK and TS_32BLK macros are bogus too. This patch fixes all these issues for sh7722 and sh7724, other CPUs stay unchanged and might need to be fixed too. Signed-off-by: Guennadi Liakhovetski Acked-by: Dan Williams Signed-off-by: Paul Mundt