kernel.git/arch/sh/include/asm/processor.h, branch linux-2.6.34.y

sh: wire up SET/GET_UNALIGN_CTL.

2010-02-23T03:56:30Z

This hooks up the SET/GET_UNALIGN_CTL knobs cribbing the bulk of it from the PPC and ia64 implementations. The thread flags happen to be the logical inverse of what the global fault mode is set to, so this works out pretty cleanly. By default the global fault mode is used, with tasks now being able to override their own settings via prctl(). Signed-off-by: Paul Mundt

sh64: Fix up the build for the thread_xstate changes.

2010-01-19T06:40:03Z

This updates the sh64 processor info with the sh32 changes in order to tie in to the generic task_xstate management code. Signed-off-by: Paul Mundt

sh: Handle early ioremaps through fixed mappings.

2010-01-18T12:08:32Z

This adds in a mem_init_done to work out when a standard ioremap() is possible, falling back to the fixmap based ioremap otherwise. Signed-off-by: Paul Mundt

Merge branch 'master' into sh/smp

2009-09-01T04:54:14Z

Conflicts: arch/sh/mm/cache-sh4.c

sh: Add initial support for SH7757 CPU subtype

2009-08-21T08:25:47Z

Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt

sh: Track the CPU family in sh_cpuinfo.

2009-08-15T01:48:13Z

This adds a family member to struct sh_cpuinfo, which allows us to fall back more on the probe routines to work out what sort of subtype we are running on. This will be used by the CPU cache initialization code in order to first do family-level initialization, followed by subtype-level optimizations. Signed-off-by: Paul Mundt

sh: rework mode pin code

2009-06-11T06:08:53Z

This patch reworks the mode pin code to keep the pin definitions in one place. The mode pins values are now the value of the bit instead of bit number. With this patch in place the sh7785 header file contains mode pin comments. The sh7785 clock code and the sh7785lcr board code are updated to reflect the new shared mode pins. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt

sh: boot word / mode pin support V2

2009-06-01T06:44:49Z

Add mode pin support for the SuperH architecture V2. With this patch applied the board code can add their own function to export the cpu mode pin configuration. In most cases this will be a constant bitmap, but boards that allow reading this from a register can instead read out the pin state from hardware. The code warns if a pin is tested but no board specific mode pin function has been provided. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt

sh: Add support for SH7724 (SH-Mobile R2R) CPU subtype.

2009-04-16T05:40:56Z

This implements initial support for the SH-Mobile R2R CPU. Based on Rev 0.11 of the initial SH7724 hardware manual. Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt

sh: Add support for SH7786 CPU subtype.

2009-03-03T06:40:25Z

This adds preliminary support for the SH7786 CPU subtype. While this is a dual-core CPU, only UP is supported for now. L2 cache support is likewise not yet implemented. More information on this particular CPU subtype is available at: http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/ Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt