<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/riscv/kernel/smp.c, branch linux-5.4.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.4.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.4.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2021-05-19T08:08:26Z</updated>
<entry>
<title>RISC-V: Fix error code returned by riscv_hartid_to_cpuid()</title>
<updated>2021-05-19T08:08:26Z</updated>
<author>
<name>Anup Patel</name>
</author>
<published>2021-04-15T08:55:22Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b8168792c3fb42136134f6cfee880f4ef2469221'/>
<id>urn:sha1:b8168792c3fb42136134f6cfee880f4ef2469221</id>
<content type='text'>
[ Upstream commit 533b4f3a789d49574e7ae0f6ececed153f651f97 ]

We should return a negative error code upon failure in
riscv_hartid_to_cpuid() instead of NR_CPUS. This is also
aligned with all uses of riscv_hartid_to_cpuid() which
expect negative error code upon failure.

Fixes: 6825c7a80f18 ("RISC-V: Add logical CPU indexing for RISC-V")
Fixes: f99fb607fb2b ("RISC-V: Use Linux logical CPU number instead of hartid")
Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>riscv: add missing header file includes</title>
<updated>2019-10-28T07:46:01Z</updated>
<author>
<name>Paul Walmsley</name>
</author>
<published>2019-10-17T22:21:28Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5ed881bc3afc40d7a23c2211ead1aeb4980dda20'/>
<id>urn:sha1:5ed881bc3afc40d7a23c2211ead1aeb4980dda20</id>
<content type='text'>
sparse identifies several missing prototypes caused by missing
preprocessor include directives:

arch/riscv/kernel/cpufeature.c:16:6: warning: symbol 'has_fpu' was not declared. Should it be static?
arch/riscv/kernel/process.c:26:6: warning: symbol 'arch_cpu_idle' was not declared. Should it be static?
arch/riscv/kernel/reset.c:15:6: warning: symbol 'pm_power_off' was not declared. Should it be static?
arch/riscv/kernel/syscall_table.c:15:6: warning: symbol 'sys_call_table' was not declared. Should it be static?
arch/riscv/kernel/traps.c:149:13: warning: symbol 'trap_init' was not declared. Should it be static?
arch/riscv/kernel/vdso.c:54:5: warning: symbol 'arch_setup_additional_pages' was not declared. Should it be static?
arch/riscv/kernel/smp.c:64:6: warning: symbol 'arch_match_cpu_phys_id' was not declared. Should it be static?
arch/riscv/kernel/module-sections.c:89:5: warning: symbol 'module_frob_arch_sections' was not declared. Should it be static?
arch/riscv/mm/context.c:42:6: warning: symbol 'switch_mm' was not declared. Should it be static?

Fix by including the appropriate header files in the appropriate
source files.

This patch should have no functional impact.

Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
</content>
</entry>
<entry>
<title>RISC-V: Export kernel symbols for kvm</title>
<updated>2019-09-20T15:36:39Z</updated>
<author>
<name>Atish Patra</name>
</author>
<published>2019-09-04T16:14:06Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d3d7a0ce020e2d14967159b5351158c80b681760'/>
<id>urn:sha1:d3d7a0ce020e2d14967159b5351158c80b681760</id>
<content type='text'>
Export a few symbols used by kvm module. Without this, kvm cannot
be compiled as a module.

Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Acked-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Reviewed-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Reviewed-by: Alexander Graf &lt;graf@amazon.com&gt;
[paul.walmsley@sifive.com: updated to apply; clarified short patch
 description]
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>riscv: cleanup riscv_cpuid_to_hartid_mask</title>
<updated>2019-09-05T08:51:57Z</updated>
<author>
<name>Christoph Hellwig</name>
</author>
<published>2019-08-21T14:58:35Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f5bf645d10f2c6cc85294021af70f2b7bcc42d8e'/>
<id>urn:sha1:f5bf645d10f2c6cc85294021af70f2b7bcc42d8e</id>
<content type='text'>
Move the initial clearing of the mask from the callers to
riscv_cpuid_to_hartid_mask, and remove the unused !CONFIG_SMP stub.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>riscv: optimize send_ipi_single</title>
<updated>2019-09-05T08:46:21Z</updated>
<author>
<name>Christoph Hellwig</name>
</author>
<published>2019-08-21T14:58:34Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e11ea2a02b93933425ddfa4b4e2012ba0882ac82'/>
<id>urn:sha1:e11ea2a02b93933425ddfa4b4e2012ba0882ac82</id>
<content type='text'>
Don't go through send_ipi_mask, but just set the op bit and then pass
a simple generated hartid mask directly to sbi_send_ipi.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
[paul.walmsley@sifive.com: minor patch description fixes]
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>riscv: cleanup send_ipi_mask</title>
<updated>2019-09-05T08:44:37Z</updated>
<author>
<name>Christoph Hellwig</name>
</author>
<published>2019-08-21T14:58:33Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1db7a7ca5ac543d0e360d1e8a3dc10ce74b58027'/>
<id>urn:sha1:1db7a7ca5ac543d0e360d1e8a3dc10ce74b58027</id>
<content type='text'>
Use the special barriers for atomic bitops to make the intention
a little more clear, and use riscv_cpuid_to_hartid_mask instead of
open coding it.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>riscv: refactor the IPI code</title>
<updated>2019-09-05T07:55:48Z</updated>
<author>
<name>Christoph Hellwig</name>
</author>
<published>2019-08-21T14:58:32Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7e0e50895fdf7d5ad94ceb6a076571f4c6a357fe'/>
<id>urn:sha1:7e0e50895fdf7d5ad94ceb6a076571f4c6a357fe</id>
<content type='text'>
This prepares for adding native non-SBI IPI code.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234</title>
<updated>2019-06-19T15:09:07Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2019-06-03T05:44:50Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=caab277b1de0a22b675c4c95fc7b285ec2eb5bf5'/>
<id>urn:sha1:caab277b1de0a22b675c4c95fc7b285ec2eb5bf5</id>
<content type='text'>
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation this program is
  distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details you should have received a copy of the gnu general
  public license along with this program if not see http www gnu org
  licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 503 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Alexios Zavras &lt;alexios.zavras@intel.com&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Reviewed-by: Enrico Weigelt &lt;info@metux.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>riscv: move flush_icache_{all,mm} to cacheflush.c</title>
<updated>2019-05-17T03:42:12Z</updated>
<author>
<name>Gary Guo</name>
</author>
<published>2019-03-27T00:41:25Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=58de77545e53b94cd6c816776197dade598632c5'/>
<id>urn:sha1:58de77545e53b94cd6c816776197dade598632c5</id>
<content type='text'>
Currently, flush_icache_all is macro-expanded into a SBI call, yet no
asm/sbi.h is included in asm/cacheflush.h. This could be moved to
mm/cacheflush.c instead (SBI call will dominate performance-wise and
there is no worry to not have it inlined.

Currently, flush_icache_mm stays in kernel/smp.c, which looks like a
hack to prevent it from being compiled when CONFIG_SMP=n. It should
also be in mm/cacheflush.c.

Signed-off-by: Gary Guo &lt;gary@garyguo.net&gt;
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Access CSRs using CSR numbers</title>
<updated>2019-05-17T03:42:11Z</updated>
<author>
<name>Anup Patel</name>
</author>
<published>2019-04-25T08:38:41Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a3182c91ef4e7dda90ff080a4132efd3ecb8786a'/>
<id>urn:sha1:a3182c91ef4e7dda90ff080a4132efd3ecb8786a</id>
<content type='text'>
We should prefer accessing CSRs using their CSR numbers because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR numbers
   as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not recognize
   newly addes CSRs by name.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
</feed>
