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<title>kernel.git/arch/riscv/kernel/setup.c, branch linux-4.19.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.19.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.19.y'/>
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<updated>2020-05-27T15:37:28Z</updated>
<entry>
<title>riscv: set max_pfn to the PFN of the last page</title>
<updated>2020-05-27T15:37:28Z</updated>
<author>
<name>Vincent Chen</name>
</author>
<published>2020-04-27T06:59:24Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=512f9837b44827736ee5da7f96dbd92dc30457c8'/>
<id>urn:sha1:512f9837b44827736ee5da7f96dbd92dc30457c8</id>
<content type='text'>
commit c749bb2d554825e007cbc43b791f54e124dadfce upstream.

The current max_pfn equals to zero. In this case, I found it caused users
cannot get some page information through /proc such as kpagecount in v5.6
kernel because of new sanity checks. The following message is displayed by
stress-ng test suite with the command "stress-ng --verbose --physpage 1 -t
1" on HiFive unleashed board.

 # stress-ng --verbose --physpage 1 -t 1
 stress-ng: debug: [109] 4 processors online, 4 processors configured
 stress-ng: info: [109] dispatching hogs: 1 physpage
 stress-ng: debug: [109] cache allocate: reducing cache level from L3 (too high) to L0
 stress-ng: debug: [109] get_cpu_cache: invalid cache_level: 0
 stress-ng: info: [109] cache allocate: using built-in defaults as no suitable cache found
 stress-ng: debug: [109] cache allocate: default cache size: 2048K
 stress-ng: debug: [109] starting stressors
 stress-ng: debug: [109] 1 stressor spawned
 stress-ng: debug: [110] stress-ng-physpage: started [110] (instance 0)
 stress-ng: error: [110] stress-ng-physpage: cannot read page count for address 0x3fd34de000 in /proc/kpagecount, errno=0 (Success)
 stress-ng: error: [110] stress-ng-physpage: cannot read page count for address 0x3fd32db078 in /proc/kpagecount, errno=0 (Success)
 ...
 stress-ng: error: [110] stress-ng-physpage: cannot read page count for address 0x3fd32db078 in /proc/kpagecount, errno=0 (Success)
 stress-ng: debug: [110] stress-ng-physpage: exited [110] (instance 0)
 stress-ng: debug: [109] process [110] terminated
 stress-ng: info: [109] successful run completed in 1.00s
 #

After applying this patch, the kernel can pass the test.

 # stress-ng --verbose --physpage 1 -t 1
 stress-ng: debug: [104] 4 processors online, 4 processors configured stress-ng: info: [104] dispatching hogs: 1 physpage
 stress-ng: info: [104] cache allocate: using defaults, can't determine cache details from sysfs
 stress-ng: debug: [104] cache allocate: default cache size: 2048K
 stress-ng: debug: [104] starting stressors
 stress-ng: debug: [104] 1 stressor spawned
 stress-ng: debug: [105] stress-ng-physpage: started [105] (instance 0) stress-ng: debug: [105] stress-ng-physpage: exited [105] (instance 0) stress-ng: debug: [104] process [105] terminated
 stress-ng: info: [104] successful run completed in 1.01s
 #

Cc: stable@vger.kernel.org
Signed-off-by: Vincent Chen &lt;vincent.chen@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Yash Shah &lt;yash.shah@sifive.com&gt;
Tested-by: Yash Shah &lt;yash.shah@sifive.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
[Palmer: back-ported to 4.19]
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>riscv: fixup max_low_pfn with PFN_DOWN.</title>
<updated>2019-03-13T21:02:27Z</updated>
<author>
<name>Guo Ren</name>
</author>
<published>2019-01-12T08:16:27Z</published>
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<id>urn:sha1:ffabf74c67967ac6c14f66d8a4f0f218c890e2cd</id>
<content type='text'>
[ Upstream commit 28198c4639b39899a728ac89aea29d2a7a72562f ]

max_low_pfn should be pfn_size not byte_size.

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Signed-off-by: Mao Han &lt;mao_han@c-sky.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>RISCV: Fix end PFN for low memory</title>
<updated>2018-10-02T19:50:01Z</updated>
<author>
<name>Atish Patra</name>
</author>
<published>2018-09-11T18:30:18Z</published>
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<id>urn:sha1:ef1f2258748b675422ca0107e5bfb9ceeac675de</id>
<content type='text'>
Use memblock_end_of_DRAM which provides correct last low memory
PFN. Without that, DMA32 region becomes empty resulting in zero
pages being allocated for DMA32.

This patch is based on earlier patch from palmer which never
merged into 4.19. I just edited the commit text to make more
sense.

Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>riscv: Do not overwrite initrd_start and initrd_end</title>
<updated>2018-09-05T00:04:50Z</updated>
<author>
<name>Guenter Roeck</name>
</author>
<published>2018-08-29T00:33:46Z</published>
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<id>urn:sha1:e866d3e84eb7c9588afb77604d417e8cc49fe216</id>
<content type='text'>
setup_initrd() overwrites initrd_start and initrd_end if __initramfs_size
is larger than 0, which is always true even if there is no embedded
initramfs. This prevents booting qemu with "-initrd" parameter.
Overwriting initrd_start and initrd_end is not necessary since
__initramfs_start and __initramfs_size are used directly in
populate_rootfs() to load the built-in initramfs, so just drop
that code.

Signed-off-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Add early printk support via the SBI console</title>
<updated>2018-08-13T15:31:30Z</updated>
<author>
<name>Palmer Dabbelt</name>
</author>
<published>2017-12-08T23:10:35Z</published>
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<id>urn:sha1:5b5c2a2c44d7225ab3abbcc7e1881b97ea9872dd</id>
<content type='text'>
This code lives entirely within the RISC-V arch code.  I've left it
within an "#ifdef CONFIG_EARLY_PRINTK" despite always having
EARLY_PRINTK support on RISC-V just in case someone wants to remove
it.

Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>riscv: remove unnecessary of_platform_populate call</title>
<updated>2018-07-04T21:12:38Z</updated>
<author>
<name>Rob Herring</name>
</author>
<published>2018-06-19T21:41:34Z</published>
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<id>urn:sha1:f67f10b8a6c96ab6c1d6946d269e2ca5f9998cc2</id>
<content type='text'>
The DT core will call of_platform_default_populate, so it is not
necessary for arch specific code to call it unless there are custom
match entries, auxdata or parent device. Neither of those apply here, so
remove the call.

Cc: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Cc: Albert Ou &lt;aou@eecs.berkeley.edu&gt;
Cc: linux-riscv@lists.infradead.org
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>riscv: add swiotlb support</title>
<updated>2018-05-19T06:46:26Z</updated>
<author>
<name>Christoph Hellwig</name>
</author>
<published>2018-04-27T06:43:14Z</published>
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<id>urn:sha1:10314e09d044296bc50dec831aa85b3ae1acedf0</id>
<content type='text'>
All RISC-V platforms today lack an IOMMU. However, legacy PCI devices
sometimes require DMA-memory to be in the low 32 bits.  To make this work,
we enable the software-based bounce buffers from swiotlb.  They only impose
overhead when the device in question cannot address the full 64-bit address
space, so a perfect fit.

This patch assumes that DMA is coherent with the processor and the PCI
bus.  It also assumes that the processor and devices share a common
address space. This is true for all RISC-V platforms so far.

[changelog stolen from an earlier patch by Palmer Dabbelt that did the
 more complicated swiotlb wireup before the recent consolidation]

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>Rename sbi_save to parse_dtb to improve code readability</title>
<updated>2018-02-20T18:56:26Z</updated>
<author>
<name>Michael Clark</name>
</author>
<published>2018-02-15T20:30:29Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8b08f50152ff85a4780e5c385d2b65889406e842'/>
<id>urn:sha1:8b08f50152ff85a4780e5c385d2b65889406e842</id>
<content type='text'>
The sbi_ prefix would seem to indicate an SBI interface, and save is not
very specific. After applying this patch, reading head.S makes more sense.

Signed-off-by: Michael Clark &lt;michaeljclark@mac.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>riscv: add ZONE_DMA32</title>
<updated>2018-01-31T03:14:27Z</updated>
<author>
<name>Christoph Hellwig</name>
</author>
<published>2018-01-16T08:37:50Z</published>
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<id>urn:sha1:5ec9c4ff0430e33b602cc0ff8ab9dec8ef548d28</id>
<content type='text'>
This patch allows devices that require memory that can be addressed
using 32-bit addresses to work easily on RISC-V systems.  The newly
improved dma-direct ops will tap into this pool automatically for
32-bit addressing.

Based on an earlier patch from Wesley W. Terpstra.

CC: Wesley W. Terpstra &lt;terpstra@sifive.com&gt;
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Remove mem_end command line processing</title>
<updated>2018-01-31T03:09:53Z</updated>
<author>
<name>Palmer Dabbelt</name>
</author>
<published>2017-12-16T19:17:16Z</published>
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<id>urn:sha1:5d44bf2065e169dd857a4207505210fce25743e6</id>
<content type='text'>
This is just some cruft left over from before the port converted to
device tree.  The right way to handle memory regions is to specify them
in the device tree, which BBL (our simplest bootloader) is already
capable of doing.  This patch simply removes the cruft.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
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