<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/riscv/kernel/head.S, branch linux-6.10.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.10.y</id>
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<updated>2024-09-12T09:13:02Z</updated>
<entry>
<title>riscv: set trap vector earlier</title>
<updated>2024-09-12T09:13:02Z</updated>
<author>
<name>yang.zhang</name>
</author>
<published>2024-05-08T02:24:45Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6ffa0fb4f842b5eea1d9e4e5b71401d6556040cf'/>
<id>urn:sha1:6ffa0fb4f842b5eea1d9e4e5b71401d6556040cf</id>
<content type='text'>
[ Upstream commit 6ad8735994b854b23c824dd6b1dd2126e893a3b4 ]

The exception vector of the booting hart is not set before enabling
the mmu and then still points to the value of the previous firmware,
typically _start. That makes it hard to debug setup_vm() when bad
things happen. So fix that by setting the exception vector earlier.

Reviewed-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
Signed-off-by: yang.zhang &lt;yang.zhang@hexintek.com&gt;
Link: https://lore.kernel.org/r/20240508022445.6131-1-gaoshanliukou@163.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>riscv: smp: fail booting up smp if inconsistent vlen is detected</title>
<updated>2024-08-03T07:00:06Z</updated>
<author>
<name>Andy Chiu</name>
</author>
<published>2024-05-09T16:26:52Z</published>
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<id>urn:sha1:1911fd52a37a294f08457892aea001f7c811c8de</id>
<content type='text'>
[ Upstream commit 38a94c46660f5612c6ef37ec9754ec1543b038cd ]

Currently we only support Vector for SMP platforms, that is, all SMP
cores have the same vlenb. If we happen to detect a mismatching vlen, it
is better to just fail bootting it up to prevent further race/scheduling
issues.

Also, move .Lsecondary_park forward and chage `tail smp_callin` into a
regular call in the early assembly. So a core would be parked right
after a return from smp_callin. Note that a successful smp_callin
does not return.

Fixes: 7017858eb2d7 ("riscv: Introduce riscv_v_vsize to record size of Vector context")
Reported-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Closes: https://lore.kernel.org/linux-riscv/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/
Signed-off-by: Andy Chiu &lt;andy.chiu@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Reviewed-by: Yunhui Cui &lt;cuiyunhui@bytedance.com&gt;
Link: https://lore.kernel.org/r/20240510-zve-detection-v5-2-0711bdd26c12@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge patch series "Fix XIP boot and make XIP testable in QEMU"</title>
<updated>2024-01-10T04:10:39Z</updated>
<author>
<name>Palmer Dabbelt</name>
</author>
<published>2024-01-10T03:33:25Z</published>
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<id>urn:sha1:2bf8acbf542bbc83a72a1c9d3f4f87aab7f2d2c1</id>
<content type='text'>
Frederik Haxel &lt;haxel@fzi.de&gt; says:

XIP boot seems to be broken for some time now. A likely reason why no one
seems to have noticed this is that XIP is more difficult to test, as it is
currently not easily testable with QEMU.

These patches fix the XIP boot and allow an XIP build without BUILTIN_DTB,
which in turn makes it easier to test an image with the QEMU virt machine.

* b4-shazam-merge:
  riscv: Allow disabling of BUILTIN_DTB for XIP
  riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro
  riscv: Make XIP bootable again

Link: https://lore.kernel.org/r/20231212130116.848530-1-haxel@fzi.de
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'palmer/fixes' into for-next</title>
<updated>2024-01-10T04:10:32Z</updated>
<author>
<name>Palmer Dabbelt</name>
</author>
<published>2024-01-10T04:10:32Z</published>
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<id>urn:sha1:5c89186a32702d35496c8d3a9d8877ea6608d30a</id>
<content type='text'>
I don't usually merge these in, but I missed sending a PR due to the
holidays.

* palmer/fixes:
  riscv: Fix set_direct_map_default_noflush() to reset _PAGE_EXEC
  riscv: Fix module_alloc() that did not reset the linear mapping permissions
  riscv: Fix wrong usage of lm_alias() when splitting a huge linear mapping
  riscv: Check if the code to patch lies in the exit section
  riscv: errata: andes: Probe for IOCP only once in boot stage
  riscv: Fix SMP when shadow call stacks are enabled
  dt-bindings: perf: riscv,pmu: drop unneeded quotes
  riscv: fix misaligned access handling of C.SWSP and C.SDSP
  RISC-V: hwprobe: Always use u64 for extension bits
  Support rv32 ULEB128 test
  riscv: Correct type casting in module loading
  riscv: Safely remove entries from relocation list

Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>riscv: Allow disabling of BUILTIN_DTB for XIP</title>
<updated>2024-01-10T03:33:22Z</updated>
<author>
<name>Frederik Haxel</name>
</author>
<published>2023-12-12T13:01:14Z</published>
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<id>urn:sha1:6c4a2f6329f0925161a80d2fd90aa8438c1ca82f</id>
<content type='text'>
This enables, among other things, testing with the QEMU virt machine.

To build an XIP kernel for the QEMU virt machine, configure the
the kernel as desired and apply the following configuration
```
CONFIG_NONPORTABLE=y
CONFIG_XIP_KERNEL=y
CONFIG_XIP_PHYS_ADDR=0x20000000
CONFIG_PHYS_RAM_BASE=0x80200000
CONFIG_BUILTIN_DTB=n
```

Since the QEMU virt flash memory expects a 32 MB file, the built image
must be padded. For example, with
`truncate -s 32M arch/riscv/boot/xipImage`

The kernel can be started using the following command in QEMU (v8+)
```
qemu-system-riscv64 -M virt,pflash0=pflash0 \
 -blockdev node-name=pflash0,driver=file,read-only=on,\
filename=arch/riscv/boot/xipImage &lt;optional parameters&gt;
```

Signed-off-by: Frederik Haxel &lt;haxel@fzi.de&gt;
Link: https://lore.kernel.org/r/20231212130116.848530-4-haxel@fzi.de
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>riscv: Make XIP bootable again</title>
<updated>2024-01-10T03:33:20Z</updated>
<author>
<name>Frederik Haxel</name>
</author>
<published>2023-12-12T13:01:12Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=66f1e68093979816a23412a3fad066f5bcbc0360'/>
<id>urn:sha1:66f1e68093979816a23412a3fad066f5bcbc0360</id>
<content type='text'>
Currently, the XIP kernel seems to fail to boot due to missing
XIP_FIXUP and a wrong page_offset value. A superfluous XIP_FIXUP
has also been removed.

Signed-off-by: Frederik Haxel &lt;haxel@fzi.de&gt;
Link: https://lore.kernel.org/r/20231212130116.848530-2-haxel@fzi.de
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>riscv: Remove unused members from struct cpu_operations</title>
<updated>2024-01-04T23:03:06Z</updated>
<author>
<name>Samuel Holland</name>
</author>
<published>2023-11-21T23:47:25Z</published>
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<id>urn:sha1:79093f3ec39c90edf4bd1a532d922ee6163441ec</id>
<content type='text'>
name is not used anywhere at all. cpu_prepare and cpu_disable do nothing
and always return 0 if implemented.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20231121234736.3489608-3-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>riscv: Fix SMP when shadow call stacks are enabled</title>
<updated>2023-12-06T15:15:19Z</updated>
<author>
<name>Samuel Holland</name>
</author>
<published>2023-11-21T21:19:29Z</published>
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<id>urn:sha1:f40cab8e18ed57d2c7b5213437d83d955f78097f</id>
<content type='text'>
This fixes two bugs in SCS initialization for secondary CPUs. First,
the SCS was not initialized at all in the spinwait boot path. Second,
the code for the SBI HSM path attempted to initialize the SCS before
enabling the MMU. However, that involves dereferencing the thread
pointer, which requires the MMU to be enabled.

Fix both issues by setting up the SCS in the common secondary entry
path, after enabling the MMU.

Fixes: d1584d791a29 ("riscv: Implement Shadow Call Stack")
Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Sami Tolvanen &lt;samitolvanen@google.com&gt;
Link: https://lore.kernel.org/r/20231121211958.3158576-1-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>riscv: Use SYM_*() assembly macros instead of deprecated ones</title>
<updated>2023-11-06T17:42:47Z</updated>
<author>
<name>Clément Léger</name>
</author>
<published>2023-10-24T13:26:52Z</published>
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<id>urn:sha1:76329c693924d8f37afbf361f0d8daab594e1644</id>
<content type='text'>
ENTRY()/END()/WEAK() macros are deprecated and we should make use of the
new SYM_*() macros [1] for better annotation of symbols. Replace the
deprecated ones with the new ones and fix wrong usage of END()/ENDPROC()
to correctly describe the symbols.

[1] https://docs.kernel.org/core-api/asm-annotations.html

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20231024132655.730417-3-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>riscv: use ".L" local labels in assembly when applicable</title>
<updated>2023-11-06T17:42:05Z</updated>
<author>
<name>Clément Léger</name>
</author>
<published>2023-10-24T13:26:51Z</published>
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<id>urn:sha1:b18f7296fbfdb2ad0871f00f3042fc74663d52ac</id>
<content type='text'>
For the sake of coherency, use local labels in assembly when
applicable. This also avoid kprobes being confused when applying a
kprobe since the size of function is computed by checking where the
next visible symbol is located. This might end up in computing some
function size to be way shorter than expected and thus failing to apply
kprobes to the specified offset.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20231024132655.730417-2-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
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