<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/riscv/Kbuild, branch linux-5.13.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.13.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.13.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2020-05-18T18:38:05Z</updated>
<entry>
<title>riscv: Allow device trees to be built into the kernel</title>
<updated>2020-05-18T18:38:05Z</updated>
<author>
<name>Palmer Dabbelt</name>
</author>
<published>2020-04-14T04:43:24Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2d2682512f0faf4d09a696184bf3c0bb6838baca'/>
<id>urn:sha1:2d2682512f0faf4d09a696184bf3c0bb6838baca</id>
<content type='text'>
Some systems don't provide a useful device tree to the kernel on boot.
Chasing around bootloaders for these systems is a headache, so instead
le't's just keep a device tree table in the kernel, keyed by the SOC's
unique identifier, that contains the relevant DTB.

This is only implemented for M mode right now. While we could implement
this via the SBI calls that allow access to these identifiers, we don't
have any systems that need this right now.

Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>riscv: add arch/riscv/Kbuild</title>
<updated>2019-08-31T00:34:00Z</updated>
<author>
<name>Masahiro Yamada</name>
</author>
<published>2019-08-21T09:26:58Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=909548d6c5789dbd6cd4c7a6b32fcf0ae974f5ee'/>
<id>urn:sha1:909548d6c5789dbd6cd4c7a6b32fcf0ae974f5ee</id>
<content type='text'>
Use the standard obj-y form to specify the sub-directories under
arch/riscv/. No functional change intended.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
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