kernel.git/arch/powerpc/sysdev/fsl_pci.c, branch linux-3.7.y

powerpc/fsl-pci: use 'Header Type' to identify PCIE mode

2012-09-27T12:31:58Z

The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, some latest silicons do not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so change code to use 'Header Type' field to judge PCIE mode. Because FSL PCI controller does not support 'Header Type', patch still uses 'Programming Interface' to identify PCI mode. Signed-off-by: Minghuan Lian Signed-off-by: Roy Zang Signed-off-by: Kumar Gala

powerpc/fsl-pci: fix warning when CONFIG_SWIOTLB is disabled

2012-09-19T13:41:46Z

Fix the following warning: arch/powerpc/sysdev/fsl_pci.c: In function 'fsl_pci_probe': arch/powerpc/sysdev/fsl_pci.c:867:25: error: unused variable 'hose' Signed-off-by: Jia Hongtao Acked-by: Michael Neuling Signed-off-by: Kumar Gala

powerpc/fsl-pci: Unify pci/pcie initialization code

2012-09-12T19:57:12Z

We unified the Freescale pci/pcie initialization by changing the fsl_pci to a platform driver. In previous PCI code architecture the initialization routine is called at board_setup_arch stage. Now the initialization is done in probe function which is architectural better. Also It's convenient for adding PM support for PCI controller in later patch. Now we registered pci controllers as platform devices. So we combine two initialization code as one platform driver. Signed-off-by: Jia Hongtao Signed-off-by: Li Yang Signed-off-by: Chunhe Lan Signed-off-by: Kumar Gala

powerpc/pci: Use PCIe IP block revision register instead of compatible

2012-09-12T19:57:12Z

Freescale PCIe IP block revision bigger than rev2.2 will also need redefine the sequence of inbound windows. So change to use IP block revision instead of compatible for the judgment. Signed-off-by: Roy Zang Signed-off-by: Kumar Gala

powerpc/swiotlb: Enable at early stage and disable if not necessary

2012-09-12T19:57:09Z

Remove the dependency on PCI initialization for SWIOTLB initialization. So that PCI can be initialized at proper time. SWIOTLB is partly determined by PCI inbound/outbound map which is assigned in PCI initialization. But swiotlb_init() should be done at the stage of mem_init() which is much earlier than PCI initialization. So we reserve the memory for SWIOTLB first and free it if not necessary. All boards are converted to fit this change. Signed-off-by: Jia Hongtao Signed-off-by: Li Yang Acked-by: Tony Breeds Signed-off-by: Kumar Gala

powerpc/fsl-pci: add fsl,qoriq-pcie-v2.4 compatible string

2012-09-12T19:57:07Z

The PCI controller on the Freescale P5040 is v2.4. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala

powerpc/fsl-pci: Only scan PCI bus if configured as a host

2012-08-03T13:25:52Z

We change fsl_add_bridge to return -ENODEV if the controller is working in agent mode. Then check the return value of fsl_add_bridge to guarantee that only successfully added host bus will be scanned. Signed-off-by: Jia Hongtao Signed-off-by: Li Yang Signed-off-by: Kumar Gala

powerpc/fsl-pci: get PCI init out of board files

2012-07-11T12:49:33Z

As an alternative incremental starting point to Jia Hongtao's patchset, get the FSL PCI init out of the board files, but do not yet convert to a platform driver. Rather than having each board supply a magic register offset for determining the "primary" bus, we look for which PCI host bridge contains an ISA node within its subtree. If there is no ISA node, normally that would mean there is no primary bus, but until certain bugs are fixed we arbitrarily designate a primary in this case. Conversion to a platform driver and related improvements can happen after this, as the ordering issues are sorted out. Signed-off-by: Scott Wood Signed-off-by: Kumar Gala

powerpc/fsl/pci: Fix when quirk_fsl_pcie_header is freed up

2012-07-10T12:07:19Z

Change quirk_fsl_pcie_header from __init to __devinit to ensure if we have a runtime access (like via an FPGA being loaded after boot on the PCIe link) that we dont access randomly freed memory. Signed-off-by: Matias Garcia Signed-off-by: Kumar Gala

powerpc/fsl/pci: Fix PCIe fixup regression

2012-02-16T05:15:03Z

Upstream changes to the way PHB resources are registered broke the resource fixup for FSL boards. We can no longer rely on the resource pointer array for the PHB's pci_bus structure, so let's leave it alone and go straight for the PHB resources instead. This also makes the code generally more readable. Signed-off-by: Benjamin Herrenschmidt