kernel.git/arch/powerpc/lib/test_emulate_step.c, branch linux-5.8.y

powerpc: Use a datatype for instructions

2020-05-18T14:10:37Z

Currently unsigned ints are used to represent instructions on powerpc. This has worked well as instructions have always been 4 byte words. However, ISA v3.1 introduces some changes to instructions that mean this scheme will no longer work as well. This change is Prefixed Instructions. A prefixed instruction is made up of a word prefix followed by a word suffix to make an 8 byte double word instruction. No matter the endianness of the system the prefix always comes first. Prefixed instructions are only planned for powerpc64. Introduce a ppc_inst type to represent both prefixed and word instructions on powerpc64 while keeping it possible to exclusively have word instructions on powerpc32. Signed-off-by: Jordan Niethe [mpe: Fix compile error in emulate_spe()] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20200506034050.24806-12-jniethe5@gmail.com

powerpc: Use an accessor for instructions

2020-05-18T14:10:36Z

In preparation for introducing a more complicated instruction type to accommodate prefixed instructions use an accessor for getting an instruction as a u32. Signed-off-by: Jordan Niethe Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20200506034050.24806-8-jniethe5@gmail.com

powerpc: Use a macro for creating instructions from u32s

2020-05-18T14:10:36Z

In preparation for instructions having a more complex data type start using a macro, ppc_inst(), for making an instruction out of a u32. A macro is used so that instructions can be used as initializer elements. Currently this does nothing, but it will allow for creating a data type that can represent prefixed instructions. Signed-off-by: Jordan Niethe [mpe: Change include guard to _ASM_POWERPC_INST_H] Signed-off-by: Michael Ellerman Reviewed-by: Alistair Popple Link: https://lore.kernel.org/r/20200506034050.24806-7-jniethe5@gmail.com

powerpc/sstep: Fix DS operand in ld encoding to appropriate value

2020-03-25T01:06:46Z

ld instruction should have 14 bit immediate field (DS) concatenated with 0b00 on the right, encode it accordingly. Introduce macro `IMM_DS()` to encode DS form instructions with 14 bit immediate field. Fixes: 4ceae137bdab ("powerpc: emulate_step() tests for load/store instructions") Reviewed-by: Sandipan Das Signed-off-by: Balamuruhan S Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20200311102405.392263-1-bala24@linux.ibm.com

powerpc/lib: Fix emulate_step() std test

2020-03-17T13:05:54Z

We should be checking that the instruction was stepped *and* that the target register has the right value. Signed-off-by: Nicholas Piggin Reviewed-by: Ravi Bangoria [mpe: Write change log] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20200226055302.1577954-1-npiggin@gmail.com

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30T18:26:32Z

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman

powerpc: sstep: Add tests for addc[.] instruction

2019-02-23T10:04:31Z

This adds test cases for the addc[.] instruction. Signed-off-by: Sandipan Das Signed-off-by: Michael Ellerman

powerpc: sstep: Add tests for add[.] instruction

2019-02-23T10:04:31Z

This adds test cases for the add[.] instruction. Signed-off-by: Sandipan Das Signed-off-by: Michael Ellerman

powerpc: sstep: Add tests for compute type instructions

2019-02-23T10:04:31Z

This enhances the current selftest framework for validating the in-kernel instruction emulation infrastructure by adding support for compute type instructions i.e. integer ALU-based instructions. Originally, this framework was limited to only testing load and store instructions. While most of the GPRs can be validated, support for SPRs is limited to LR, CR and XER for now. When writing the test cases, one must ensure that the Stack Pointer (GPR1) or the Thread Pointer (GPR13) are not touched by any means as these are vital non-volatile registers. Signed-off-by: Sandipan Das [mpe: Use patch_site for the code patching] Signed-off-by: Michael Ellerman

powerpc/sstep: Fix emulate_step test if VSX not present

2018-06-03T14:39:14Z

emulate_step() tests are failing if VSX is not supported or disabled. emulate_step_test: lxvd2x : FAIL emulate_step_test: stxvd2x : FAIL If !CPU_FTR_VSX, emulate_step() failure is expected and testcase should PASS with a valid justification. After patch: emulate_step_test: lxvd2x : PASS (!CPU_FTR_VSX) emulate_step_test: stxvd2x : PASS (!CPU_FTR_VSX) Signed-off-by: Ravi Bangoria Signed-off-by: Michael Ellerman