kernel.git/arch/powerpc/kernel/head_64.S, branch linux-2.6.25.y

[POWERPC] Fix iSeries hard irq enabling regression

2008-04-03T11:10:34Z

A subtle bug sneaked into iSeries recently. On this platform, we must not normally clear MSR:EE (the hardware external interrupt enable) except for short periods of time. Taking an interrupt while soft-disabled doesn't cause us to clear it for example. The iSeries kernel expects to mostly run with MSR:EE enabled at all times except in a few exception entry/exit code paths. Thus local_irq_enable() doesn't check if it needs to hard-enable as it expects this to be unnecessary on iSeries. However, hard_irq_disable() _does_ cause MSR:EE to be cleared, including on iSeries. A call to it was recently added to the context switch code, thus causing interrupts to become disabled for a long periods of time, causing the iSeries watchdog to kick in under some circumstances and other nasty things. This patch fixes it by making local_irq_enable() properly re-enable MSR:EE on iSeries. It basically removes a return statement here to make iSeries use the same code path as everybody else. That does mean that we might occasionally get spurious decrementer interrupts but I don't think that matters. Another option would have been to make hard_irq_disable() a nop on iSeries but I didn't like it much, in case we have good reasons to hard-disable. Part of the patch is fixes to make sure the hard_enabled PACA field is properly set on iSeries as it used not to be before, since it was mostly unused. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Paul Mackerras

[POWERPC] Provide a way to protect 4k subpages when using 64k pages

2008-01-23T23:06:01Z

Using 64k pages on 64-bit PowerPC systems makes life difficult for emulators that are trying to emulate an ISA, such as x86, which use a smaller page size, since the emulator can no longer use the MMU and the normal system calls for controlling page protections. Of course, the emulator can emulate the MMU by checking and possibly remapping the address for each memory access in software, but that is pretty slow. This provides a facility for such programs to control the access permissions on individual 4k sub-pages of 64k pages. The idea is that the emulator supplies an array of protection masks to apply to a specified range of virtual addresses. These masks are applied at the level where hardware PTEs are inserted into the hardware page table based on the Linux PTEs, so the Linux PTEs are not affected. Note that this new mechanism does not allow any access that would otherwise be prohibited; it can only prohibit accesses that would otherwise be allowed. This new facility is only available on 64-bit PowerPC and only when the kernel is configured for 64k pages. The masks are supplied using a new subpage_prot system call, which takes a starting virtual address and length, and a pointer to an array of protection masks in memory. The array has a 32-bit word per 64k page to be protected; each 32-bit word consists of 16 2-bit fields, for which 0 allows any access (that is otherwise allowed), 1 prevents write accesses, and 2 or 3 prevent any access. Implicit in this is that the regions of the address space that are protected are switched to use 4k hardware pages rather than 64k hardware pages (on machines with hardware 64k page support). In fact the whole process is switched to use 4k hardware pages when the subpage_prot system call is used, but this could be improved in future to switch only the affected segments. The subpage protection bits are stored in a 3 level tree akin to the page table tree. The top level of this tree is stored in a structure that is appended to the top level of the page table tree, i.e., the pgd array. Since it will often only be 32-bit addresses (below 4GB) that are protected, the pointers to the first four bottom level pages are also stored in this structure (each bottom level page contains the protection bits for 1GB of address space), so the protection bits for addresses below 4GB can be accessed with one fewer loads than those for higher addresses. Signed-off-by: Paul Mackerras

[POWERPC] Fix si_addr value on low level hash failures

2007-11-08T03:15:34Z

If the low level MMU hash table insertion returns an error (which can happen in some rare circumstances when the hypervisor refuses the insertion of a PTE, typically if you try to access junk via /dev/mem), the generated signal had an incorrect si_addr value due to a bug in the assembly, which was loading it as a 32 bits quantity instead of a 64 bits quantity. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Paul Mackerras

[POWERPC] Use 1TB segments

2007-10-12T04:05:17Z

This makes the kernel use 1TB segments for all kernel mappings and for user addresses of 1TB and above, on machines which support them (currently POWER5+, POWER6 and PA6T). We detect that the machine supports 1TB segments by looking at the ibm,processor-segment-sizes property in the device tree. We don't currently use 1TB segments for user addresses < 1T, since that would effectively prevent 32-bit processes from using huge pages unless we also had a way to revert to using 256MB segments. That would be possible but would involve extra complications (such as keeping track of which segment size was used when HPTEs were inserted) and is not addressed here. Parts of this patch were originally written by Ben Herrenschmidt. Signed-off-by: Paul Mackerras

[POWERPC] FWNMI is only used on pSeries

2007-09-19T05:25:34Z

This saves 4k on non pSeries builds (except for iSeries where it saves almost 4k). Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras

[POWERPC] Size swapper_pg_dir correctly

2007-09-19T05:25:34Z

David Gibson pointed out that swapper_pg_dir actually need to be PGD_TABLE_SIZE bytes long not PAGE_SIZE. This actually saves 64k in the bss for a kernel ppc64_defconfig built with CONFIG_PPC_64K_PAGES. Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras

[POWERPC] Remove cmd_line from head*.S

2007-09-19T05:25:34Z

It is just a C char array, so declare it thusly. Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras

[POWERPC] Move lowlevel runlatch calls under cpu feature control

2007-09-13T15:33:22Z

There's no need to call the runlatch on functions on processors that don't implement them (CPU_FTR_CTRL). Signed-off-by: Olof Johansson Signed-off-by: Paul Mackerras

[POWERPC] Move the iSeries exception vectors

2007-08-22T06:48:35Z

out of head_64.S and into platforms/iseries/exception.S Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras

[POWERPC] Move the exception macros into a header file

2007-08-22T06:48:35Z

It makes head_64.S a bit more readable and will allow us to move the iSeries exceptions elsewhere. This also removes the last line of the comment: * The following macros define the code that appears as * the prologue to each of the exception handlers. They * are split into two parts to allow a single kernel binary * to be used for pSeries and iSeries. * LOL. One day... - paulus Anything is possible. :-) Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras